Palkesh Jain

Publication Activity (10 Years)

Years Active: 2006-2023
Publications (10 Years): 13

Top Topics

Environmentally Friendly

Reliability Analysis

Microscope Images

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Vidya A. Chhabria, Vipul Ahuja, Ashwath Prabhu, Nikhil Patil, Palkesh Jain, Sachin S. Sapatnekar
Encoder-Decoder Networks for Analyzing Thermal and Power Delivery Networks. ACM Trans. Design Autom. Electr. Syst. 28 (1) (2023)
Vidya A. Chhabria, Vipul Ahuja, Ashwath Prabhu, Nikhil Patil, Palkesh Jain, Sachin S. Sapatnekar
Encoder-Decoder Networks for Analyzing Thermal and Power Delivery Networks. CoRR (2021)
Vidya A. Chhabria, Vipul Ahuja, Ashwath Prabhu, Nikhil Patil, Palkesh Jain, Sachin S. Sapatnekar
Thermal and IR Drop Analysis Using Convolutional Encoder-Decoder Networks. ASP-DAC (2021)
Vidya A. Chhabria, Vipul Ahuja, Ashwath Prabhu, Nikhil Patil, Palkesh Jain, Sachin S. Sapatnekar
Thermal and IR Drop Analysis Using Convolutional Encoder-Decoder Networks. CoRR (2020)
Shashank Varshney, Hameedah Sultan, Palkesh Jain, Smruti R. Sarangi
NanoTherm: An Analytical Fourier-Boltzmann Framework for Full Chip Thermal Simulations. ICCAD (2019)
Palkesh Jain, Vivek Mishra, Sachin S. Sapatnekar
Fast Stochastic Analysis of Electromigration in Power Distribution Networks. IEEE Trans. Very Large Scale Integr. Syst. 25 (9) (2017)
Vivek Mishra, Palkesh Jain, Sravan K. Marella, Sachin S. Sapatnekar
Incorporating the Role of Stress on Electromigration in Power Grids with Via Arrays. DAC (2017)
Palkesh Jain, Jordi Cortadella, Sachin S. Sapatnekar
A Fast and Retargetable Framework for Logic-IP-Internal Electromigration Assessment Comprehending Advanced Waveform Effects. IEEE Trans. Very Large Scale Integr. Syst. 24 (6) (2016)
Gracieli Posser, Vivek Mishra, Palkesh Jain, Ricardo Reis, Sachin S. Sapatnekar
Cell-Internal Electromigration: Analysis and Pin Placement Based Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (2) (2016)
Palkesh Jain, Sachin S. Sapatnekar, Jordi Cortadella
A retargetable and accurate methodology for logic-IP-internal electromigration assessment. ASP-DAC (2015)
Gracieli Posser, Vivek Mishra, Palkesh Jain, Ricardo Reis, Sachin S. Sapatnekar
Impact on performance, power, area and wirelength using electromigration-aware cells. ICECS (2015)
Gracieli Posser, Lucas de Paris, Vivek Mishra, Palkesh Jain, Ricardo Reis, Sachin S. Sapatnekar
Reducing the signal Electromigration effects on different logic gates by cell layout optimization. LASCAS (2015)
Palkesh Jain, Sachin S. Sapatnekar, Jordi Cortadella
Stochastic and topologically aware electromigration analysis for clock skew. IRPS (2015)
Palkesh Jain, Bapana Pudi, Meghna Sreenivasan
Design-in-reliability: From library modeling and optimization to gate-level verification. Microelectron. Reliab. 54 (6-7) (2014)
Palkesh Jain, Frank Cano, Bapana Pudi, N. V. Arvind
Asymmetric Aging: Introduction and Solution for Power-Managed Mixed-Signal SoCs. IEEE Trans. Very Large Scale Integr. Syst. 22 (3) (2014)
Gracieli Posser, Vivek Mishra, Palkesh Jain, Ricardo Reis, Sachin S. Sapatnekar
A systematic approach for analyzing and optimizing cell-internal signal electromigration. ICCAD (2014)
Palkesh Jain, Ankit Jain
Accurate Current Estimation for Interconnect Reliability Analysis. IEEE Trans. Very Large Scale Integr. Syst. 20 (9) (2012)
Palkesh Jain, Ankit Jain
Accurate Estimation of Signal Currents for Reliability Analysis Considering Advanced Waveform-Shape Effects. VLSI Design (2011)
Palkesh Jain, D. Vinay Kumar, J. M. Vasi, Mahesh B. Patil
Evaluation of Non-Quasi-Static Effects during SEU in Deep-Submicron MOS Devices and Circuits. VLSI Design (2006)