Gracieli Posser

Publication Activity (10 Years)

Years Active: 2010-2023
Publications (10 Years): 8

Top Topics

Mixed Integer Linear Programs

Design Automation

Lagrangian Relaxation

Top Venues

Publications

Iris Hui-Ru Jiang, David G. Chinnery, Gracieli Posser, Jens Lienig
Introduction to the Special Section on Advances in Physical Design Automation. ACM Trans. Design Autom. Electr. Syst. 28 (5) (2023)
Gracieli Posser, Evangeline F. Y. Young, Stephan Held, Yih-Lang Li, David Z. Pan
Challenges and Approaches in VLSI Routing. ISPD (2022)
Wen-Hao Liu, Stefanus Mantik, Wing-Kai Chow, Yixiao Ding, Amin Farshidi, Gracieli Posser
ISPD 2019 Initial Detailed Routing Contest and Benchmark with Advanced Routing Rules. ISPD (2019)
Stefanus Mantik, Gracieli Posser, Wing-Kai Chow, Yixiao Ding, Wen-Hao Liu
ISPD 2018 Initial Detailed Routing Contest and Benchmarks. ISPD (2018)
Gracieli Posser, Vivek Mishra, Palkesh Jain, Ricardo Reis, Sachin S. Sapatnekar
Cell-Internal Electromigration: Analysis and Pin Placement Based Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (2) (2016)
Lucas de Paris, Gracieli Posser, Ricardo Reis
Electromigration aware circuits by using special signal non-default routing rules. ISCAS (2016)
Calebe Conceição, Gracieli Posser, Ricardo Reis
Reducing the number of transistors with gate clustering. LASCAS (2016)
Alexandra L. Zimpeck, Cristina Meinhardt, Gracieli Posser, Ricardo Augusto da Luz Reis
FinFET cells with different transistor sizing techniques against PVT variations. ISCAS (2016)
Gracieli Posser, Vivek Mishra, Palkesh Jain, Ricardo Reis, Sachin S. Sapatnekar
Impact on performance, power, area and wirelength using electromigration-aware cells. ICECS (2015)
Gracieli Posser, Lucas de Paris, Vivek Mishra, Palkesh Jain, Ricardo Reis, Sachin S. Sapatnekar
Reducing the signal Electromigration effects on different logic gates by cell layout optimization. LASCAS (2015)
Alexandra L. Zimpeck, Cristina Meinhardt, Gracieli Posser, Ricardo Reis
Process variability in FinFET standard cells with different transistor sizing techniques. ICECS (2015)
Gracieli Posser, Vivek Mishra, Ricardo Augusto da Luz Reis, Sachin S. Sapatnekar
Analyzing the electromigration effects on different metal layers and different wire lengths. ICECS (2014)
Guilherme Flach, Tiago Reimann, Gracieli Posser, Marcelo O. Johann, Ricardo Reis
Effective Method for Simultaneous Gate Sizing and $V$ th Assignment Using Lagrangian Relaxation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (4) (2014)
Gracieli Posser, Jozeanne Belomo, Cristina Meinhardt, Ricardo Augusto da Luz Reis
Perfomance Improvement with Dedicated Transistor Sizing for MOSFET and FinFET Devices. ISVLSI (2014)
Gracieli Posser, Vivek Mishra, Palkesh Jain, Ricardo Reis, Sachin S. Sapatnekar
A systematic approach for analyzing and optimizing cell-internal signal electromigration. ICCAD (2014)
Guilherme Flach, Tiago Reimann, Gracieli Posser, Marcelo O. Johann, Ricardo Reis
Simultaneous gate sizing and Vth assignment using Lagrangian Relaxation and delay sensitivities. ISVLSI (2013)
Tiago Reimann, Gracieli Posser, Guilherme Flach, Marcelo O. Johann, Ricardo Reis
Simultaneous gate sizing and Vt assignment using Fanin/Fanout ratio and Simulated Annealing. ISCAS (2013)
Gracieli Posser, Guilherme Flach, Gustavo Wilke, Ricardo Reis
Transistor sizing and gate sizing using geometric programming considering delay minimization. NEWCAS (2012)
Gracieli Posser, Guilherme Flach, Gustavo Wilke, Ricardo Reis
Gate Sizing Minimizing Delay and Area. ISVLSI (2011)
Gracieli Posser, Adriel Ziesemer, Daniel Guimares Jr., Gustavo Wilke, Ricardo A. L. Reis
A study on layout quality of automatic generated cells. ICECS (2010)