Evangeline F. Y. Young

ORCID

Publication Activity (10 Years)

Years Active: 1999-2024
Publications (10 Years): 98

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

DAC

ICCAD

ISPD

Publications

Qijing Wang, Jinwei Liu, Martin D. F. Wong, Evangeline F. Y. Young
A Multi-agent Generative Model for Collaborative Global Routing Refinement. ACM Great Lakes Symposium on VLSI (2024)
Xinshi Zang, Qin Luo, Zhongwei Shao, Jifeng Zhang, Evangeline F. Y. Young, Martin D. F. Wong
Dynamic Multi-FPGA Prototyping Platforms with Simultaneous Networking, Placement and Routing. ACM Great Lakes Symposium on VLSI (2024)
Fangzhou Wang, Jinwei Liu, Wing Ho Lau, Haocheng Li, Evangeline F. Y. Young
FastPass: A Fast Pin Access Analysis Framework for Detailed Routability Enhancement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (5) (2024)
Bangqi Fu, Lixin Liu, Yang Sun, Wing Ho Lau, Martin D. F. Wong, Evangeline F. Y. Young
CoPlace: Coherent Placement Engine with Layout-aware Partitioning for 3D ICs. ASPDAC (2024)
Lei Chen, Yiqi Chen, Zhufei Chu, Wenji Fang, Tsung-Yi Ho, Yu Huang, Sadaf Khan, Min Li, Xingquan Li, Yun Liang, Yibo Lin, Jinwei Liu, Yi Liu, Guojie Luo, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue, Evangeline F. Y. Young, Bei Yu, Mingxuan Yuan, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, Sunan Zou
The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models. CoRR (2024)
Tianji Liu, Qijing Wang, Lixin Liu, Fangzhou Wang, Evangeline F. Y. Young
On Advanced Methodologies for Microarchitecture Design Space Exploration. ACM Great Lakes Symposium on VLSI (2024)
Xinshi Zang, Wenhao Lin, Shiju Lin, Jinwei Liu, Evangeline F. Y. Young
An Open-Source Fast Parallel Routing Approach for Commercial FPGAs. ACM Great Lakes Symposium on VLSI (2024)
Evangeline F. Y. Young
Recap of the 42nd Edition of the International Conference on Computer- Aided Design (ICCAD 2023). IEEE Des. Test 41 (2) (2024)
Tianji Liu, Lei Chen, Xing Li, Mingxuan Yuan, Evangeline F. Y. Young
FineMap: A Fine-grained GPU-parallel LUT Mapping Engine. ASPDAC (2024)
Lixin Liu, Tianji Liu, Bentian Jiang, Evangeline F. Y. Young
Parmesan: Efficient Partitioning and Mapping Flow for DNN Training on General Device Topology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (8) (2024)
Fangzhou Wang, Qijing Wang, Lilas Alrahis, Bangqi Fu, Shui Jiang, Xiaopeng Zhang, Ozgur Sinanoglu, Tsung-Yi Ho, Evangeline F. Y. Young, Johann Knechtel
TroLLoc: Logic Locking and Layout Hardening for IC Security Closure against Hardware Trojans. CoRR (2024)
Lixin Liu, Bangqi Fu, Shiju Lin, Jinwei Liu, Evangeline F. Y. Young, Martin D. F. Wong
Xplace: An Extremely Fast and Extensible Placement Framework. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (6) (2024)
Xinshi Zang, Wenhao Lin, Shiju Lin, Jinwei Liu, Evangeline F. Y. Young
An Open-Source Fast Parallel Routing Approach for Commercial FPGAs. CoRR (2024)
Evangeline F. Y. Young
Accelerating Physical Design from 1 to N. ISPD (2024)
Qijing Wang, Xiaopeng Zhang, Martin D. F. Wong, Evangeline F. Y. Young
ControLayout: Conditional Diffusion for Style-Controllable and Violation-Fixable Layout Pattern Generation. ACM Great Lakes Symposium on VLSI (2024)
Shiju Lin, Jinwei Liu, Evangeline F. Y. Young, Martin D. F. Wong
GAMER: GPU-Accelerated Maze Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (2) (2023)
Tianji Liu, Evangeline F. Y. Young
Rethinking AIG Resynthesis in Parallel. DAC (2023)
Xinshi Zang, Evangeline F. Y. Young, Martin D. F. Wong
SPARK: A Scalable Partitioning and Routing Framework for Multi-FPGA Systems. ACM Great Lakes Symposium on VLSI (2023)
Jinwei Liu, Evangeline F. Y. Young
EDGE: Efficient DAG-based Global Routing Engine. DAC (2023)
Jingsong Chen, Jian Kuang, Guowei Zhao, Dennis J.-H. Huang, Evangeline F. Y. Young
PROS 2.0: A Plug-In for Routability Optimization and Routed Wirelength Estimation Using Deep Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (1) (2023)
Evangeline F. Y. Young
GPU Acceleration in Physical Synthesis. ISPD (2023)
Fangzhou Wang, Qijing Wang, Bangqi Fu, Shui Jiang, Xiaopeng Zhang, Lilas Alrahis, Ozgur Sinanoglu, Johann Knechtel, Tsung-Yi Ho, Evangeline F. Y. Young
Security Closure of IC Layouts Against Hardware Trojans. ISPD (2023)
Xinshi Zang, Lei Chen, Xing Li, Wilson W. K. Thong, Weihua Sheng, Evangeline F. Y. Young, Martin D. F. Wong
CPP: A Multi-Level Circuit Partitioning Predictor for Hardware Verification Systems. ACM Great Lakes Symposium on VLSI (2023)
Bentian Jiang, Xinshi Zang, Martin D. F. Wong, Evangeline F. Y. Young
Exploring Rule-Free Layout Decomposition via Deep Reinforcement Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (9) (2023)
Dan Zheng, Evangeline F. Y. Young
An Integrated Circuit Partitioning and TDM Assignment Optimization Framework for Multi-FPGA Systems. ASP-DAC (2023)
Fangzhou Wang, Jinwei Liu, Evangeline F. Y. Young
FastPass: Fast Pin Access Analysis with Incremental SAT Solving. ISPD (2023)
Fangzhou Wang, Qijing Wang, Bangqi Fu, Shui Jiang, Xiaopeng Zhang, Lilas Alrahis, Ozgur Sinanoglu, Johann Knechtel, Tsung-Yi Ho, Evangeline F. Y. Young
Security Closure of IC Layouts Against Hardware Trojans. CoRR (2022)
Jinwei Liu, Xiaopeng Zhang, Shiju Lin, Xinshi Zang, Jingsong Chen, Bentian Jiang, Martin D. F. Wong, Evangeline F. Y. Young
Partition and place finite element model on wafer-scale engine. DAC (2022)
Shiju Lin, Jinwei Liu, Tianji Liu, Martin D. F. Wong, Evangeline F. Y. Young
NovelRewrite: node-level parallel AIG rewriting. DAC (2022)
Haocheng Li, Wing-Kai Chow, Gengjie Chen, Bei Yu, Evangeline F. Y. Young
Pin-Accessible Legalization for Mixed-Cell-Height Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (1) (2022)
Bentian Jiang, Lixin Liu, Yuzhe Ma, Bei Yu, Evangeline F. Y. Young
Neural-ILT 2.0: Migrating ILT to Domain-Specific and Multitask-Enabled Neural Network. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (8) (2022)
Bentian Jiang, Jingsong Chen, Jinwei Liu, Lixin Liu, Fangzhou Wang, Xiaopeng Zhang, Evangeline F. Y. Young
CU.POKer: Placing DNNs on WSE With Optimal Kernel Sizing and Efficient Protocol Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (6) (2022)
Xiaopeng Zhang, Shoubo Hu, Zhitang Chen, Shengyu Zhu, Evangeline F. Y. Young, Pengyun Li, Cheng Chen, Yu Huang, Jianye Hao
RCANet: Root Cause Analysis via Latent Variable Interaction Modeling for Yield Improvement. ITC (2022)
Qijing Wang, Bentian Jiang, Martin D. F. Wong, Evangeline F. Y. Young
A2-ILT: GPU accelerated ILT with spatial attention mechanism. DAC (2022)
Gracieli Posser, Evangeline F. Y. Young, Stephan Held, Yih-Lang Li, David Z. Pan
Challenges and Approaches in VLSI Routing. ISPD (2022)
Lixin Liu, Bangqi Fu, Martin D. F. Wong, Evangeline F. Y. Young
Xplace: an extremely fast and extensible global placement framework. DAC (2022)
Haoyu Yang, Shifan Zhang, Kang Liu, Siting Liu, Benjamin Tan, Ramesh Karri, Siddharth Garg, Bei Yu, Evangeline F. Y. Young
Attacking a CNN-based Layout Hotspot Detector Using Group Gradient Method. ASP-DAC (2021)
Xiaopeng Zhang, Haoyu Yang, Evangeline F. Y. Young
Attentional Transfer is All You Need: Technology-aware Layout Pattern Generation. DAC (2021)
Jinwei Liu, Gengjie Chen, Evangeline F. Y. Young
REST: Constructing Rectilinear Steiner Minimum Tree via Reinforcement Learning. DAC (2021)
Dan Zheng, Xiaopeng Zhang, Chak-Wa Pui, Evangeline F. Y. Young
Multi-FPGA Co-optimization: Hybrid Routing and Competitive-based Time Division Multiplexing Assignment. ASP-DAC (2021)
Bentian Jiang, Xiaopeng Zhang, Lixin Liu, Evangeline F. Y. Young
Building up End-to-end Mask Optimization Framework with Self-training. ISPD (2021)
Haocheng Li, Satwik Patnaik, Mohammed Ashraf, Haoyu Yang, Johann Knechtel, Bei Yu, Ozgur Sinanoglu, Evangeline F. Y. Young
Deep Learning Analysis for Split-Manufactured Layouts With Routing Perturbation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (10) (2021)
Haoyu Yang, Shuhe Li, Zihao Deng, Yuzhe Ma, Bei Yu, Evangeline F. Y. Young
GAN-OPC: Mask Optimization With Lithography-Guided Generative Adversarial Nets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (10) (2020)
Jingsong Chen, Jian Kuang, Guowei Zhao, Dennis J.-H. Huang, Evangeline F. Y. Young
PROS: A Plug-in for Routability Optimization applied in the State-of-the-art commercial EDA tool using deep learning. ICCAD (2020)
Kang Liu, Haoyu Yang, Yuzhe Ma, Benjamin Tan, Bei Yu, Evangeline F. Y. Young, Ramesh Karri, Siddharth Garg
Adversarial Perturbation Attacks on ML-based CAD: A Case Study on CNN-based Lithographic Hotspot Detection. ACM Trans. Design Autom. Electr. Syst. 25 (5) (2020)
Gengjie Chen, Evangeline F. Y. Young
SALT: Provably Good Routing Topology by a Novel Steiner Shallow-Light Tree Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (6) (2020)
Peishan Tu, Chak-Wa Pui, Evangeline F. Y. Young
Simultaneous Reconnection Surgery Technique of Routing With Machine Learning-Based Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (6) (2020)
Jinwei Liu, Chak-Wa Pui, Fangzhou Wang, Evangeline F. Y. Young
CUGR: Detailed-Routability-Driven 3D Global Routing with Probabilistic Resource Model. DAC (2020)
Xiaopeng Zhang, James Shiely, Evangeline F. Y. Young
Layout Pattern Generation and Legalization with Generative Learning Models. ICCAD (2020)
Gengjie Chen, Chak-Wa Pui, Haocheng Li, Evangeline F. Y. Young
Dr. CU: Detailed Routing by Sparse Grid Graph and Minimum-Area-Captured Path Search. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (9) (2020)
Bentian Jiang, Lixin Liu, Yuzhe Ma, Hang Zhang, Bei Yu, Evangeline F. Y. Young
Neural-ILT: Migrating ILT to Neural Networks for Mask Printability and Complexity Co-optimization. ICCAD (2020)
Chak-Wa Pui, Evangeline F. Y. Young
Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA Systems. ACM Trans. Design Autom. Electr. Syst. 25 (2) (2020)
Bentian Jiang, Jingsong Chen, Jinwei Liu, Lixin Liu, Fangzhou Wang, Xiaopeng Zhang, Evangeline F. Y. Young
CU.POKer: Placing DNNs on Wafer-Scale Al Accelerator with Optimal Kernel Sizing. ICCAD (2020)
Haocheng Li, Satwik Patnaik, Abhrajit Sengupta, Haoyu Yang, Johann Knechtel, Bei Yu, Evangeline F. Y. Young, Ozgur Sinanoglu
Attacking Split Manufacturing from a Deep Learning Perspective. CoRR (2020)
Jingsong Chen, Jinwei Liu, Gengjie Chen, Dan Zheng, Evangeline F. Y. Young
MARCH: MAze Routing Under a Concurrent and Hierarchical Scheme for Buses. DAC (2019)
Haocheng Li, Gengjie Chen, Bentian Jiang, Jingsong Chen, Evangeline F. Y. Young
Dr. CU 2.0: A Scalable Detailed Routing Framework with Correct-by-Construction Design Rule Satisfaction. ICCAD (2019)
Jian Kuang, Evangeline F. Y. Young
Fixed-Parameter Tractable Algorithms for Optimal Layout Decomposition and Beyond. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (9) (2019)
Ilgweon Kang, Fang Qiao, Dongwon Park, Daniel Kane, Evangeline F. Y. Young, Chung-Kuan Cheng, Ronald L. Graham
Three-dimensional Floorplan Representations by Using Corner Links and Partial Order. ACM Trans. Design Autom. Electr. Syst. 24 (1) (2019)
Haoyu Yang, Jing Su, Yi Zou, Yuzhe Ma, Bei Yu, Evangeline F. Y. Young
Layout Hotspot Detection With Feature Tensor Generation and Deep Biased Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (6) (2019)
Haocheng Li, Satwik Patnaik, Abhrajit Sengupta, Haoyu Yang, Johann Knechtel, Bei Yu, Evangeline F. Y. Young, Ozgur Sinanoglu
Attacking Split Manufacturing from a Deep Learning Perspective. DAC (2019)
Kang Liu, Haoyu Yang, Yuzhe Ma, Benjamin Tan, Bei Yu, Evangeline F. Y. Young, Ramesh Karri, Siddharth Garg
Are Adversarial Perturbations a Showstopper for ML-Based CAD? A Case Study on CNN-Based Lithographic Hotspot Detection. CoRR (2019)
Bentian Jiang, Xiaopeng Zhang, Ran Chen, Gengjie Chen, Peishan Tu, Wei Li, Evangeline F. Y. Young, Bei Yu
FIT: Fill Insertion Considering Timing. DAC (2019)
Bentian Jiang, Hang Zhang, Jinglei Yang, Evangeline F. Y. Young
A fast machine learning-based mask printability predictor for OPC acceleration. ASP-DAC (2019)
Gengjie Chen, Evangeline F. Y. Young
Dim Sum: Light Clock Tree by Small Diameter Sum. DATE (2019)
Gengjie Chen, Chak-Wa Pui, Haocheng Li, Jingsong Chen, Bentian Jiang, Evangeline F. Y. Young
Detailed routing by sparse grid graph and minimum-area-captured path search. ASP-DAC (2019)
Chak-Wa Pui, Evangeline F. Y. Young
Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA Systems. ICCAD (2019)
Chak-Wa Pui, Gang Wu, Freddy Y. C. Mang, Evangeline F. Y. Young
An Analytical Approach for Time-Division Multiplexing Optimization in Multi-FPGA based Systems. SLIP (2019)
Evangeline F. Y. Young
Session details: Patterning and Machine Learning. ISPD (2019)
Peishan Tu, Chak-Wa Pui, Evangeline F. Y. Young
Simultaneous Timing Driven Tree Surgery in Routing with Machine Learning-based Acceleration. ACM Great Lakes Symposium on VLSI (2018)
Haoyu Yang, Shuhe Li, Yuzhe Ma, Bei Yu, Evangeline F. Y. Young
GAN-OPC: mask optimization with lithography-guided generative adversarial nets. DAC (2018)
Chak-Wa Pui, Peishan Tu, Haocheng Li, Gengjie Chen, Evangeline F. Y. Young
A two-step search engine for large scale boolean matching under NP3 equivalence. ASP-DAC (2018)
Jian Kuang, Evangeline F. Y. Young, Bei Yu
CRMA: Incorporating Cut Redistribution With Mask Assignment to Enable the Fabrication of 1-D Gridded Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (10) (2018)
Jian Kuang, Junjie Ye, Evangeline F. Y. Young
STOMA: Simultaneous Template Optimization and Mask Assignment for Directed Self-Assembly Lithography With Multiple Patterning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (6) (2018)
Steve Dai, Yuan Zhou, Hang Zhang, Ecenur Ustun, Evangeline F. Y. Young, Zhiru Zhang
Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning. FCCM (2018)
Haocheng Li, Wing-Kai Chow, Gengjie Chen, Evangeline F. Y. Young, Bei Yu
Routability-driven and fence-aware legalization for mixed-cell-height circuits. DAC (2018)
Gengjie Chen, Chak-Wa Pui, Wing-Kai Chow, Ka-Chun Lam, Jian Kuang, Evangeline F. Y. Young, Bei Yu
RippleFPGA: Routability-Driven Simultaneous Packing and Placement for Modern FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (10) (2018)
Haoyu Yang, Yajun Lin, Bei Yu, Evangeline F. Y. Young
Lithography hotspot detection: From shallow to deep learning. SoCC (2017)
Peishan Tu, Wing-Kai Chow, Evangeline F. Y. Young
Timing driven routing tree construction. SLIP (2017)
Jian Kuang, Evangeline F. Y. Young
Fixed-Parameter Tractable Algorithms for Optimal Layout Decomposition and Beyond. DAC (2017)
Chak-Wa Pui, Gengjie Chen, Yuzhe Ma, Evangeline F. Y. Young, Bei Yu
Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper). ICCAD (2017)
Haoyu Yang, Jing Su, Yi Zou, Bei Yu, Evangeline F. Y. Young
Layout Hotspot Detection with Feature Tensor Generation and Deep Biased Learning. DAC (2017)
Hang Zhang, Fengyuan Zhu, Haocheng Li, Evangeline F. Y. Young, Bei Yu
Bilinear Lithography Hotspot Detection. ISPD (2017)
Wing-Kai Chow, Jian Kuang, Peishan Tu, Evangeline F. Y. Young
Fence-aware detailed-routability driven placement. SLIP (2017)
Gengjie Chen, Jian Kuang, Zhiliang Zeng, Hang Zhang, Evangeline F. Y. Young, Bei Yu
Minimizing Thermal Gradient and Pumping Power in 3D IC Liquid Cooling Network Design. DAC (2017)
Gengjie Chen, Peishan Tu, Evangeline F. Y. Young
SALT: Provably good routing topology by a novel steiner shallow-light tree algorithm. ICCAD (2017)
Hang Zhang, Haoyu Yang, Bei Yu, Evangeline F. Y. Young
VLSI layout hotspot detection based on discriminative feature extraction. APCCAS (2016)
Hang Zhang, Bei Yu, Evangeline F. Y. Young
Enabling online learning in lithography hotspot detection with information-theoretic feature optimization. ICCAD (2016)
Jian Kuang, Wing-Kai Chow, Evangeline F. Y. Young
Triple Patterning Lithography Aware Optimization and Detailed Placement Algorithms for Standard Cell-Based Designs. IEEE Trans. Very Large Scale Integr. Syst. 24 (4) (2016)
Jian Kuang, Evangeline F. Y. Young
Row-structure stencil planning approaches for E-beam lithography with overlapped characters. Integr. 55 (2016)
Wing-Kai Chow, Evangeline F. Y. Young
Placement: From Wirelength to Detailed Routability. IPSJ Trans. Syst. LSI Des. Methodol. 9 (2016)
Evangeline F. Y. Young, Azadeh Davoodi
Preface to Special Section on New Physical Design Techniques for the Next Generation of Integration Technology. ACM Trans. Design Autom. Electr. Syst. 21 (3) (2016)
Jian Kuang, Evangeline F. Y. Young
Optimization for Multiple Patterning Lithography with cutting process and beyond. DATE (2016)
Chak-Wa Pui, Gengjie Chen, Wing-Kai Chow, Ka-Chun Lam, Jian Kuang, Peishan Tu, Hang Zhang, Evangeline F. Y. Young, Bei Yu
RippleFPGA: a routability-driven placement for large-scale heterogeneous FPGAs. ICCAD (2016)
Xu He, Yao Wang, Yang Guo, Evangeline F. Y. Young
Ripple 2.0: Improved Movement of Cells in Routability-Driven Placement. ACM Trans. Design Autom. Electr. Syst. 22 (1) (2016)
Chuangwen Liu, Peishan Tu, Pangbo Wu, Haomo Tang, Yande Jiang, Jian Kuang, Evangeline F. Y. Young
An Effective Chemical Mechanical Polishing Fill Insertion Approach. ACM Trans. Design Autom. Electr. Syst. 21 (3) (2016)
Wing-Kai Chow, Chak-Wa Pui, Evangeline F. Y. Young
Legalization algorithm for multiple-row height standard cell design. DAC (2016)
Jian Kuang, Evangeline F. Y. Young, Bei Yu
Incorporating cut redistribution with mask assignment to enable 1D gridded design. ICCAD (2016)
Jian Kuang, Junjie Ye, Evangeline F. Y. Young
Simultaneous template optimization and mask assignment for DSA with multiple patterning. ASP-DAC (2016)
Jian Kuang, Wing-Kai Chow, Evangeline F. Y. Young
A robust approach for process variation aware mask optimization. DATE (2015)
Chuangwen Liu, Peishan Tu, Pangbo Wu, Haomo Tang, Yande Jiang, Jian Kuang, Evangeline F. Y. Young
An Effective Chemical Mechanical Polishing Filling Approach. ISVLSI (2015)

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Publication Activity (10 Years)

Top Topics

Top Venues

Evangeline F. Y. Young