Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper).
Chak-Wa PuiGengjie ChenYuzhe MaEvangeline F. Y. YoungBei YuPublished in: ICCAD (2017)
Keyphrases
- invited paper
- machine learning
- high speed
- prediction accuracy
- machine learning methods
- hardware design
- data analysis
- low cost
- real time
- power consumption
- databases
- learning algorithm
- predictive modeling
- prediction model
- learning systems
- machine learning algorithms
- data mining
- low power
- hardware implementation
- field programmable gate array
- carefully reviewed and selected from submissions
- support vector machine
- computer science