Steve Dai

Publication Activity (10 Years)

Years Active: 2010-2023
Publications (10 Years): 29

Top Topics

Design Methodologies

Symbolic Reasoning

Uniform Quantization

Top Venues

Publications

Steve Dai, Hasan Genc, Rangharajan Venkatesan, Brucek Khailany
Efficient Transformer Inference with Statically Structured Sparse Attention. DAC (2023)
Ben Keller, Rangharajan Venkatesan, Steve Dai, Stephen G. Tell, Brian Zimmer, Charbel Sakr, William J. Dally, C. Thomas Gray, Brucek Khailany
A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm. IEEE J. Solid State Circuits 58 (4) (2023)
Nan Wu, Yingjie Li, Cong Hao, Steve Dai, Cunxi Yu, Yuan Xie
Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks. CoRR (2023)
Nan Wu, Yingjie Li, Cong Hao, Steve Dai, Cunxi Yu, Yuan Xie
Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks. DAC (2023)
Charbel Sakr, Steve Dai, Rangharajan Venkatesan, Brian Zimmer, William J. Dally, Brucek Khailany
Optimal Clipping and Magnitude-aware Differentiation for Improved Quantization-aware Training. ICML (2022)
Jiawei Zhao, Steve Dai, Rangharajan Venkatesan, Brian Zimmer, Mustafa Fayez Ali, Ming-Yu Liu, Brucek Khailany, William J. Dally, Anima Anandkumar
LNS-Madam: Low-Precision Training in Logarithmic Number System Using Multiplicative Weight Update. IEEE Trans. Computers 71 (12) (2022)
Charbel Sakr, Steve Dai, Rangharajan Venkatesan, Brian Zimmer, William J. Dally, Brucek Khailany
Optimal Clipping and Magnitude-aware Differentiation for Improved Quantization-aware Training. CoRR (2022)
Ben Keller, Rangharajan Venkatesan, Steve Dai, Stephen G. Tell, Brian Zimmer, William J. Dally, C. Thomas Gray, Brucek Khailany
A 17-95.6 TOPS/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nm. VLSI Technology and Circuits (2022)
Jacob R. Stevens, Rangharajan Venkatesan, Steve Dai, Brucek Khailany, Anand Raghunathan
Softermax: Hardware/Software Co-Design of an Efficient Softmax for Transformers. CoRR (2021)
Steve Dai, Rangharajan Venkatesan, Mark Ren, Brian Zimmer, William J. Dally, Brucek Khailany
VS-Quant: Per-vector Scaled Quantization for Accurate Low-Precision Neural Network Inference. MLSys (2021)
Dillon Huff, Steve Dai, Pat Hanrahan
Clockwork: Resource-Efficient Static Scheduling for Multi-Rate Image Processing Applications on FPGAs. FCCM (2021)
Steve Dai, Rangharajan Venkatesan, Haoxing Ren, Brian Zimmer, William J. Dally, Brucek Khailany
VS-Quant: Per-vector Scaled Quantization for Accurate Low-Precision Neural Network Inference. CoRR (2021)
Steve Dai, Alicia Klinefelter, Haoxing Ren, Rangharajan Venkatesan, Ben Keller, Nathaniel Ross Pinckney, Brucek Khailany
Verifying High-Level Latency-Insensitive Designs with Formal Model Checking. CoRR (2021)
Jacob R. Stevens, Rangharajan Venkatesan, Steve Dai, Brucek Khailany, Anand Raghunathan
Softermax: Hardware/Software Co-Design of an Efficient Softmax for Transformers. DAC (2021)
Jiawei Zhao, Steve Dai, Rangharajan Venkatesan, Ming-Yu Liu, Brucek Khailany, Bill Dally, Anima Anandkumar
Low-Precision Training in Logarithmic Number System using Multiplicative Weight Update. CoRR (2021)
Dillon Huff, Steve Dai, Pat Hanrahan
Clockwork: Resource-Efficient Static Scheduling for Multi-Rate Image Processing Applications on FPGAs. FPGA (2021)
Brucek Khailany, Haoxing Ren, Steve Dai, Saad Godil, Ben Keller, Robert Kirby, Alicia Klinefelter, Rangharajan Venkatesan, Yanqing Zhang, Bryan Catanzaro, William J. Dally
Accelerating Chip Design With Machine Learning. IEEE Micro 40 (6) (2020)
Austin Rovinski, Chun Zhao, Khalid Al-Hawaj, Paul Gao, Shaolin Xie, Christopher Torng, Scott Davidson, Aporva Amarnath, Luis Vega, Bandhav Veluri, Anuj Rao, Tutu Ajayi, Julian Puscar, Steve Dai, Ritchie Zhao, Dustin Richmond, Zhiru Zhang, Ian Galton, Christopher Batten, Michael B. Taylor, Ronald G. Dreslinski
A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS. VLSI Circuits (2019)
Rangharajan Venkatesan, Yakun Sophia Shao, Miaorong Wang, Jason Clemons, Steve Dai, Matthew Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Yanqing Zhang, Brian Zimmer, William J. Dally, Joel S. Emer, Stephen W. Keckler, Brucek Khailany
MAGNet: A Modular Accelerator Generator for Neural Networks. ICCAD (2019)
Steve Dai, Zhiru Zhang
Improving Scalability of Exact Modulo Scheduling with Specialized Conflict-Driven Learning. DAC (2019)
Steve Dai, Gai Liu, Zhiru Zhang
A Scalable Approach to Exact Resource-Constrained Scheduling Based on a Joint SDC and SAT Formulation. FPGA (2018)
Zhenghong Jiang, Steve Dai, G. Edward Suh, Zhiru Zhang
High-level synthesis with timing-sensitive information flow enforcement. ICCAD (2018)
Scott Davidson, Shaolin Xie, Christopher Torng, Khalid Al-Hawaj, Austin Rovinski, Tutu Ajayi, Luis Vega, Chun Zhao, Ritchie Zhao, Steve Dai, Aporva Amarnath, Bandhav Veluri, Paul Gao, Anuj Rao, Gai Liu, Rajesh K. Gupta, Zhiru Zhang, Ronald G. Dreslinski, Christopher Batten, Michael B. Taylor
The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips. IEEE Micro 38 (2) (2018)
Yuan Zhou, Udit Gupta, Steve Dai, Ritchie Zhao, Nitish Kumar Srivastava, Hanchen Jin, Joseph Featherston, Yi-Hsiang Lai, Gai Liu, Gustavo Angarita Velasquez, Wenping Wang, Zhiru Zhang
Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAs. FPGA (2018)
Steve Dai, Yuan Zhou, Hang Zhang, Ecenur Ustun, Evangeline F. Y. Young, Zhiru Zhang
Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning. FCCM (2018)
Nitish Kumar Srivastava, Steve Dai, Rajit Manohar, Zhiru Zhang
Accelerating Face Detection on Programmable SoC Using C-Based Synthesis. FPGA (2017)
Steve Dai, Ritchie Zhao, Gai Liu, Shreesha Srinath, Udit Gupta, Christopher Batten, Zhiru Zhang
Dynamic Hazard Resolution for Pipelining Irregular Loops in High-Level Synthesis. FPGA (2017)
Gai Liu, Mingxing Tan, Steve Dai, Ritchie Zhao, Zhiru Zhang
Architecture and Synthesis for Area-Efficient Pipelining of Irregular Loop Nests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (11) (2017)
Steve Dai, Gai Liu, Ritchie Zhao, Zhiru Zhang
Enabling adaptive loop pipelining in high-level synthesis. ACSSC (2017)
Zhiru Zhang, Deming Chen, Steve Dai, Keith A. Campbell
High-level Synthesis for Low-power Design. IPSJ Trans. Syst. LSI Des. Methodol. 8 (2015)
Mingxing Tan, Gai Liu, Ritchie Zhao, Steve Dai, Zhiru Zhang
ElasticFlow: A Complexity-Effective Approach for Pipelining Irregular Loop Nests. ICCAD (2015)
Ritchie Zhao, Mingxing Tan, Steve Dai, Zhiru Zhang
Area-efficient pipelining for FPGA-targeted high-level synthesis. DAC (2015)
Mingxing Tan, Steve Dai, Udit Gupta, Zhiru Zhang
Mapping-Aware Constrained Scheduling for LUT-Based FPGAs. FPGA (2015)
Mingxing Tan, Bin Liu, Steve Dai, Zhiru Zhang
Multithreaded pipeline synthesis for data-parallel kernels. ICCAD (2014)
Steve Dai, Mingxing Tan, Kecheng Hao, Zhiru Zhang
Flushing-Enabled Loop Pipelining for High-Level Synthesis. DAC (2014)
Steve Dai, Ye Tian, Joyce E. Farrell
Design, simulation, and evaluation of imaging oximeters. Digital Photography (2013)
Hsiang-Yu Chen, Jaeyoung Park, Steve Dai, Hong Z. Tan
Design and Evaluation of Identifiable Key-Click Signals for Mobile Devices. IEEE Trans. Haptics 4 (4) (2011)
Hsiang-Yu Chen, Jaeyoung Park, Hong Z. Tan, Steve Dai
Redundant coding of simulated tactile key clicks with audio signals. HAPTICS (2010)