Dustin Richmond

Publication Activity (10 Years)

Years Active: 2013-2024
Publications (10 Years): 21

Top Topics

Field Programmable Gate Array

Heterogeneous Systems

Special Session

Top Venues

Publications

Dai Cheol Jung, Max Ruttenberg, Paul Gao, Scott Davidson, Daniel Petrisko, Kangli Li, Aditya K. Kamath, Lin Cheng, Shaolin Xie, Peitian Pan, Zhongyuan Zhao, Zichao Yue, Bandhav Veluri, Sripathi Muralitharan, Adrian Sampson, Andrew Lumsdaine, Zhiru Zhang, Christopher Batten, Mark Oskin, Dustin Richmond, Michael Bedford Taylor
Scalable, Programmable and Dense: The HammerBlade Open-Source RISC-V Manycore. ISCA (2024)
Rui-Jie Zhu, Yu Zhang, Ethan Sifferman, Tyler Sheaves, Yiqiao Wang, Dustin Richmond, Peng Zhou, Jason K. Eshraghian
Scalable MatMul-free Language Modeling. CoRR (2024)
Colin Drewes, Olivia Weng, Andres Meza, Alric Althoff, David Kohlbrenner, Ryan Kastner, Dustin Richmond
Pentimento: Data Remanence in Cloud FPGAs. ASPLOS (2) (2024)
Colin Drewes, Olivia Weng, Keegan Ryan, Bill Hunter, Christopher McCarty, Ryan Kastner, Dustin Richmond
Turn on, Tune in, Listen up: Maximizing Side-Channel Recovery in Time-to-Digital Converters. FPGA (2023)
Lin Cheng, Max Ruttenberg, Dai Cheol Jung, Dustin Richmond, Michael B. Taylor, Mark Oskin, Christopher Batten
Beyond Static Parallel Loops: Supporting Dynamic Task Parallelism on Manycore Architectures with Software-Managed Scratchpad Memories. ASPLOS (3) (2023)
Colin Drewes, Olivia Weng, Andres Meza, Alric Althoff, David Kohlbrenner, Ryan Kastner, Dustin Richmond
Pentimento: Data Remanence in Cloud FPGAs. CoRR (2023)
Lin Cheng, Peitian Pan, Zhongyuan Zhao, Krithik Ranjan, Jack Weber, Bandhav Veluri, Seyed Borna Ehsani, Max Ruttenberg, Dai Cheol Jung, Preslav Ivanov, Dustin Richmond, Michael B. Taylor, Zhiru Zhang, Christopher Batten
A Tensor Processing Framework for CPU-Manycore Heterogeneous Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (6) (2022)
Mustafa S. Gobulukoglu, Colin Drewes, Bill Hunter, Dustin Richmond, Ryan Kastner
Classifying Computations on Multi-Tenant FPGAs. FPGA (2021)
Colin Drewes, Steven Harris, Winnie Wang, Richard Appen, Olivia Weng, Ryan Kastner, William Hunter, Christopher McCarty, Dustin Richmond
A Tunable Dual-Edge Time-to-Digital Converter. FCCM (2021)
Mustafa S. Gobulukoglu, Colin Drewes, William Hunter, Ryan Kastner, Dustin Richmond
Classifying Computations on Multi-Tenant FPGAs. DAC (2021)
Ajay Brahmakshatriya, Emily Furst, Victor A. Ying, Claire Hsu, Changwan Hong, Max Ruttenberg, Yunming Zhang, Dai Cheol Jung, Dustin Richmond, Michael B. Taylor, Julian Shun, Mark Oskin, Daniel Sánchez, Saman P. Amarasinghe
Taming the Zoo: The Unified GraphIt Compiler Framework for Novel Architectures. ISCA (2021)
Michael Bedford Taylor, Luis Vega, Moein Khazraee, Ikuo Magaki, Scott Davidson, Dustin Richmond
ASIC clouds: specializing the datacenter for planet-scale applications. Commun. ACM 63 (7) (2020)
Dai Cheol Jung, Scott Davidson, Chun Zhao, Dustin Richmond, Michael Bedford Taylor
Ruche Networks: Wire-Maximal, No-Fuss NoCs : Special Session Paper. NOCS (2020)
Daniel Petrisko, Chun Zhao, Scott Davidson, Paul Gao, Dustin Richmond, Michael Bedford Taylor
NoC Symbiosis : (Special Session Paper). NOCS (2020)
Austin Rovinski, Chun Zhao, Khalid Al-Hawaj, Paul Gao, Shaolin Xie, Christopher Torng, Scott Davidson, Aporva Amarnath, Luis Vega, Bandhav Veluri, Anuj Rao, Tutu Ajayi, Julian Puscar, Steve Dai, Ritchie Zhao, Dustin Richmond, Zhiru Zhang, Ian Galton, Christopher Batten, Michael B. Taylor, Ronald G. Dreslinski
A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS. VLSI Circuits (2019)
Brennan Cain, Zain Merchant, Indira Avendano, Dustin Richmond, Ryan Kastner
PynqCopter - An Open-source FPGA Overlay for UAVs. IEEE BigData (2018)
Dustin Richmond, Michael Barrow, Ryan Kastner
Everyone's a Critic: A Tool for Exploring RISC-V Projects. FPL (2018)
Dustin Richmond, Alric Althoff, Ryan Kastner
Synthesizable Higher-Order Functions for C++. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (11) (2018)
Dajung Lee, Alric Althoff, Dustin Richmond, Ryan Kastner
A streaming clustering approach using a heterogeneous system for big data analysis. ICCAD (2017)
Janarbek Matai, Dustin Richmond, Dajung Lee, Zac Blair, Qiongzhi Wu, Amin Abazari, Ryan Kastner
Resolve: Generation of High-Performance Sorting Architectures from High-Level Synthesis. FPGA (2016)
Dustin Richmond, Jeremy Blackstone, Matthew Hogains, Kevin Thai, Ryan Kastner
Tinker: Generating Custom Memory Architectures for Altera's OpenCL Compiler. FCCM (2016)
Matthew Jacobsen, Dustin Richmond, Matthew Hogains, Ryan Kastner
RIFFA 2.1: A Reusable Integration Framework for FPGA Accelerators. ACM Trans. Reconfigurable Technol. Syst. 8 (4) (2015)
Quentin Gautier, Alexandria Shearer, Janarbek Matai, Dustin Richmond, Pingfan Meng, Ryan Kastner
Real-time 3D reconstruction for FPGAs: A case study for evaluating the performance, area, and programmability trade-offs of the Altera OpenCL SDK. FPT (2014)
Janarbek Matai, Dustin Richmond, Dajung Lee, Ryan Kastner
Enabling FPGAs for the Masses. CoRR (2014)
Dustin Richmond, Ryan Kastner, Ali Irturk, John McGarry
A FPGA design for high speed feature extraction from a compressed measurement stream. FPL (2013)