Ian Galton

Publication Activity (10 Years)

Years Active: 1989-2024
Publications (10 Years): 24

Top Topics

Frequency Distribution

Adaptive Filter

Noise Cancellation

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE J. Solid State Circuits

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Aditi Jain, Eric Fogleman, Paul Botros, Ritwik Vatsyayan, Corentin Pochet, Andrew Bourhis, Zhaoyi Liu, Suhas Chethan, Hanh-Phuc Le, Ian Galton, Shadi A. Dayeh, Drew A. Hall
A 2.5-20kSps in-Pixel Direct Digitization Front-End for ECoG with In-Stimulation Recording. CICC (2024)
Subin Kim, Ian Galton
Adaptive Cancellation of Inter-Symbol Interference in High-Speed Continuous-Time DACs. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (11) (2023)
Eslam Helal, Amr I. Eissa, Ian Galton
DTC Linearization via Mismatch-Noise Cancellation for Digital Fractional-N PLLs. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (12) (2022)
Jason Remple, Andrea Panigada, Ian Galton
An ISI Scrambling Technique for Dynamic Element Matching Current-Steering DACs. IEEE J. Solid State Circuits 57 (2) (2022)
Eslam Helal, Enrique Alvarez-Fontecilla, Amr I. Eissa, Ian Galton
A Time Amplifier Assisted Frequency-to-Digital Converter Based Digital Fractional-N PLL. IEEE J. Solid State Circuits 56 (9) (2021)
Enrique Alvarez-Fontecilla, Eslam Helal, Amr I. Eissa, Ian Galton
Spectral Breathing and Its Mitigation in Digital Fractional-N PLLs. IEEE J. Solid State Circuits 56 (10) (2021)
Enrique Alvarez-Fontecilla, Amr I. Eissa, Eslam Helal, Colin Weltin-Wu, Ian Galton
Delta-Sigma FDC Enhancements for FDC-Based Digital Fractional-N PLLs. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (3) (2021)
Derui Kong, Ian Galton
MSE Analysis of a Multi-Loop LMS Pseudo-Random Noise Canceler for Mixed-Signal Circuit Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2020)
Austin Rovinski, Chun Zhao, Khalid Al-Hawaj, Paul Gao, Shaolin Xie, Christopher Torng, Scott Davidson, Aporva Amarnath, Luis Vega, Bandhav Veluri, Anuj Rao, Tutu Ajayi, Julian Puscar, Steve Dai, Ritchie Zhao, Dustin Richmond, Zhiru Zhang, Ian Galton, Christopher Batten, Michael B. Taylor, Ronald G. Dreslinski
A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS. VLSI Circuits (2019)
Ian Galton, Colin Weltin-Wu
Understanding Phase Error and Jitter: Definitions, Implications, Simulations, and Measurement. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2019)
Derui Kong, Ian Galton
Subsampling Mismatch Noise Cancellation for High-Speed Continuous-Time DACs. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2019)
Derui Kong, Kevin Rivas-Rivera, Ian Galton
A 600-MS/s DAC With Over 87-dB SFDR and 77-dB Peak SNDR Enabled by Adaptive Cancellation of Static and Dynamic Mismatch Error. IEEE J. Solid State Circuits 54 (8) (2019)
Enrique Alvarez-Fontecilla, Christian Venerus, Ian Galton
Multi-Rate DEM With Mismatch-Noise Cancellation for DCOs in Digital PLLs. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2018)
Derui Kong, Ian Galton
Adaptive Cancellation of Static and Dynamic Mismatch Error in Continuous-Time DACs. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2018)
Jason Remple, Ian Galton
The Effects of Inter-Symbol Interference in Dynamic Element Matching DACs. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2017)
Eythan Familier, Ian Galton
Second and third-order successive requantizers for spurious tone reduction in low-noise fractional-N PLLs. CICC (2017)
Christian Venerus, Jason Remple, Ian Galton
Simplified Logic for Tree-Structure Segmented DEM Encoders. IEEE Trans. Circuits Syst. II Express Briefs (11) (2016)
Eythan Familier, Ian Galton
Second and Third-Order Noise Shaping Digital Quantizers for Low Phase Noise and Nonlinearity-Induced Spurious Tones in Fractional-N PLLs. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2016)
Colin Weltin-Wu, Guobi Zhao, Ian Galton
25.1 A highly-digital frequency synthesizer using ring-oscillator frequency-to-digital conversion and noise cancellation. ISSCC (2015)
Colin Weltin-Wu, Eythan Familier, Ian Galton
A Linearized Model for the Design of Fractional-N Digital PLLs Based on Dual-Mode Ring Oscillator FDCs. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2015)
Colin Weltin-Wu, Guobi Zhao, Ian Galton
A 3.5 GHz Digital Fractional-N PLL Frequency Synthesizer Based on Ring Oscillator Frequency-to-Digital Conversion. IEEE J. Solid State Circuits 50 (12) (2015)
Christian Venerus, Ian Galton
A TDC-Free Mostly-Digital FDC-PLL Frequency Synthesizer With a 2.8-3.5 GHz DCO. IEEE J. Solid State Circuits 50 (2) (2015)
Christian Venerus, Ian Galton
Quantization Noise Cancellation for FDC-Based Fractional-N PLLs. IEEE Trans. Circuits Syst. II Express Briefs (12) (2015)
Christian Venerus, Ian Galton
Errata for "A TDC-Free Mostly-Digital FDC-PLL Frequency Synthesizer With a 2.8-3.5 GHz DCO". IEEE J. Solid State Circuits 50 (9) (2015)
Gerry Taylor, Ian Galton
A Reconfigurable Mostly-Digital Delta-Sigma ADC With a Worst-Case FOM of 160 dB. IEEE J. Solid State Circuits 48 (4) (2013)
Nevena Rakuljic, Ian Galton
Suppression of Quantization-Induced Convergence Error in Pipelined ADCs With Harmonic Distortion Correction. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2013)
Eythan Familier, Christian Venerus, Ian Galton
A Class of Quantizers With DC-Free Quantization Noise and Optimal Immunity to Nonlinearity-Induced Spurious Tones. IEEE Trans. Signal Process. 61 (17) (2013)
Christian Venerus, Ian Galton
Delta-Sigma FDC Based Fractional-N PLLs. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2013)
Eythan Familier, Ian Galton
A Fundamental Limitation of DC-Free Quantization Noise With Respect To Nonlinearity-Induced Spurious Tones. IEEE Trans. Signal Process. 61 (16) (2013)
Gerry Taylor, Ian Galton
A reconfigurable mostly-digital ΔΣ ADC with a worst-case FOM of 160dB. VLSIC (2012)
Gerry Taylor, Ian Galton
Correction to "A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC" [Nov 10 2250-2261]. IEEE J. Solid State Circuits 46 (5) (2011)
Kevin J. Wang, Ian Galton
A Discrete-Time Model for the Design of Type-II PLLs With Passive Sampled Loop Filters. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2011)
Ian Galton
Why Dynamic-Element-Matching DACs Work. IEEE Trans. Circuits Syst. II Express Briefs (2) (2010)
Nevena Rakuljic, Ian Galton
Tree-Structured DEM DACs with Arbitrary Numbers of Levels. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2010)
Gerry Taylor, Ian Galton
A mostly digital variable-rate continuous-time ADC ΔΣ modulator. ISSCC (2010)
Ian Galton, Behzad Razavi, John Cowles, Peter R. Kinget
CMOS phase-locked loops for frequency synthesis. ISSCC (2010)
Gerry Taylor, Ian Galton
A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC. IEEE J. Solid State Circuits 45 (12) (2010)
Andrea Panigada, Ian Galton
A 130 mW 100 MS/s Pipelined ADC With 69 dB SNDR Enabled by Digital Harmonic Distortion Correction. IEEE J. Solid State Circuits 44 (12) (2009)
Ian Galton
Low-voltage analog and mixed-signal CMOS circuit design. ISSCC (2009)
Andrea Panigada, Ian Galton
A 130mW 100MS/s pipelined ADC with 69dB SNDR enabled by digital harmonic distortion correction. ISSCC (2009)
Kevin J. Wang, Ashok Swaminathan, Ian Galton
Spurious Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4 GHz Fractional-N PLL. IEEE J. Solid State Circuits 43 (12) (2008)
Kevin J. Wang, Ashok Swaminathan, Ian Galton
Spurious -Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4GHz Fractional-N PLL. ISSCC (2008)
Kok Lim Chan, Nevena Rakuljic, Ian Galton
Segmented Dynamic Element Matching for High-Resolution Digital-to-Analog Conversion. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2008)
Ian Galton, Jonathan Audy, Vadim Ivanov, Stefan Rusu, Seth R. Sanders
Short Course. ISSCC (2008)
Kok Lim Chan, Jianyu Zhu, Ian Galton
Dynamic Element Matching to Prevent Nonlinear Distortion From Pulse-Shape Mismatches in High-Resolution DACs. IEEE J. Solid State Circuits 43 (9) (2008)
Ashok Swaminathan, Kevin J. Wang, Ian Galton
A Wide-Bandwidth 2.4 GHz ISM Band Fractional-N PLL With Adaptive Phase Noise Cancellation. IEEE J. Solid State Circuits 42 (12) (2007)
Ashok Swaminathan, Kevin J. Wang, Ian Galton
A Wide-Bandwidth 2.4GHz ISM-Band Fractional-N PLL with Adaptive Phase-Noise Cancellation. ISSCC (2007)
Sudhakar Pamarti, Ian Galton
LSB Dithering in MASH Delta-Sigma D/A Converters. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2007)
Sudhakar Pamarti, Jared Welz, Ian Galton
Statistics of the Quantization Noise in 1-Bit Dithered Single-Quantizer Digital Delta-Sigma Modulators. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2007)
Ashok Swaminathan, Andrea Panigada, Elias Masry, Ian Galton
A Digital Requantizer With Shaped Requantization Noise That Remains Well Behaved After Nonlinear Distortion. IEEE Trans. Signal Process. 55 (11) (2007)
Ian Galton, Matt Miller, Robert Bogdan Staszewski, Bram Nauta, Michiel Steyaert
Analog, Mixed-Signal, and RF Circuit Design in Nanometer CMOS. ISSCC (2007)
Kok Lim Chan, Ian Galton
A 14b 100MS/s DAC with Fully Segmented Dynamic Element Matching. ISSCC (2006)
Andrea Panigada, Ian Galton
Digital Background Correction of Harmonic Distortion in Pipelined ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2006)
Sudhakar Pamarti, Lars C. Jansson, Ian Galton
Addition to "A Wideband 2.4-GHz Delta-Sigma Fractional-$N$PLL With 1-Mb/s In-Loop Modulation". IEEE J. Solid State Circuits 40 (2) (2005)
Sheng Ye, Ian Galton
Techniques for phase noise suppression in recirculating DLLs. IEEE J. Solid State Circuits 39 (8) (2004)
Eric Siragusa, Ian Galton
A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC. IEEE J. Solid State Circuits 39 (12) (2004)
Sudhakar Pamarti, Lars C. Jansson, Ian Galton
A wideband 2.4-GHz delta-sigma fractional-NPLL with 1-Mb/s in-loop modulation. IEEE J. Solid State Circuits 39 (1) (2004)
Jared Welz, Ian Galton
A tight signal-band power bound on mismatch noise in a mismatch-shaping digital-to-analog converter. IEEE Trans. Inf. Theory 50 (4) (2004)
Ian Galton
Editorial. IEEE Trans. Circuits Syst. II Express Briefs 50 (12) (2003)
Sudhakar Pamarti, Ian Galton
Phase-noise cancellation design tradeoffs in delta-sigma fractional-N PLLs. IEEE Trans. Circuits Syst. II Express Briefs 50 (11) (2003)
Sheng Ye, Lars C. Jansson, Ian Galton
Techniques for in-band phase noise suppression in re-circulating DLLs. CICC (2003)
Jared Welz, Ian Galton
A necessary and sufficient condition for mismatch shaping in multi-bit DACs. ISCAS (1) (2002)
Sheng Ye, Lars C. Jansson, Ian Galton
A multiple-crystal interface PLL with VCO realignment to reduce phase noise. IEEE J. Solid State Circuits 37 (12) (2002)
A. Fishov, E. Siragusa, Jared Welz, E. Fogleman, Ian Galton
Segmented mismatch-shaping D/A conversion. ISCAS (4) (2002)
Jorge Grilo, Ian Galton, Kevin J. Wang, Raymond Montemayor
A 12-mW ADC delta-sigma modulator with 80 dB of dynamic range integrated in a single-chip Bluetooth transceiver. IEEE J. Solid State Circuits 37 (3) (2002)
Jared Welz, Ian Galton
The mismatch-noise PSD from a tree-structured DAC in a second-order ΔΣ modulator with a midscale input. ICASSP (2001)
Jorge Grilo, Ian Galton, Kevin Wang, Raymond Montemayor
A 12 mW ADC delta-sigma modulator with 80 dB of dynamic range integrated in a single-chip Bluetooth transceiver. CICC (2001)
Eric Fogleman, Jared Welz, Ian Galton
An audio ADC Delta-Sigma modulator with 100-dB peak SINAD and 102-dB DR using a second-order mismatch-shaping DAC. IEEE J. Solid State Circuits 36 (3) (2001)
Eric Fogleman, Jared Welz, Ian Galton
An audio ADC delta-sigma modulator with 100 dB SINAD and 102 dB DR using a second-order mismatch-shaping DAC. CICC (2000)
Eric Fogleman, Ian Galton, William Huff, Henrik Jensen
A 3.3-V single-poly CMOS audio ADC delta-sigma modulator with 98-dB peak SINAD and 105-dB peak SFDR. IEEE J. Solid State Circuits 35 (3) (2000)
E. Fogleman, Ian Galton, Henrik T. Jensen
A dynamic element matching technique for reduced-distortion multibit quantization in delta-sigma ADCs. ISCAS (2) (1999)
E. Fogleman, Ian Galton, Henrik T. Jensen
An area-efficient differential input ADC with digital common mode rejection. ISCAS (2) (1999)
Eric Fogleman, Ian Galton, William Huff, Henrik Jensen
A 3.3 V single-poly CMOS audio ADC delta-sigma modulator with 98 dB peak SINAD. CICC (1999)
Ian Galton, William Huff, Paolo Carbone, Eric Siragusa
A delta-sigma PLL for 14-b, 50 kSample/s frequency-to-digital conversion of a 10 MHz FM signal. IEEE J. Solid State Circuits 33 (12) (1998)
Eric T. King, Aria Eshraghi, Ian Galton, Terri S. Fiez
A Nyquist-rate delta-sigma A/D converter. IEEE J. Solid State Circuits 33 (1) (1998)
Ian Galton
A Practical Second-Order Delta-Digma Frequency-to-Digital Converter. ISCAS (1995)
Henrik T. Jensen, Ian Galton
A Robust Parallel Delta-Sigma A/D Converter Architecture. ISCAS (1995)
Ian Galton
Granular quantization noise in a class of delta-sigma modulators. IEEE Trans. Inf. Theory 40 (3) (1994)
Ian Galton
Higher-Order Delta-Sigma Frequency to Digital Conversion. ISCAS (1994)
Ian Galton
One-bit Dithering in Delta-Sigma Modulator-based D/A Conversion. ISCAS (1993)
Ian Galton, George Zimmerman
Combined RF Phase Extraction and Digitalization. ISCAS (1993)
Ian Galton
Granular quantization noise in the first-order delta-sigma modulator. IEEE Trans. Inf. Theory 39 (6) (1993)
Ian Galton
An efficient three-point arc algorithm. IEEE Computer Graphics and Applications 9 (6) (1989)