Colin Weltin-Wu

Publication Activity (10 Years)

Years Active: 2008-2021
Publications (10 Years): 2

Top Topics

Noise Cancellation

Digital Signal Processor

Markup Language

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE J. Solid State Circuits

Publications

Enrique Alvarez-Fontecilla, Amr I. Eissa, Eslam Helal, Colin Weltin-Wu, Ian Galton
Delta-Sigma FDC Enhancements for FDC-Based Digital Fractional-N PLLs. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (3) (2021)
Ian Galton, Colin Weltin-Wu
Understanding Phase Error and Jitter: Definitions, Implications, Simulations, and Measurement. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2019)
Colin Weltin-Wu, Guobi Zhao, Ian Galton
25.1 A highly-digital frequency synthesizer using ring-oscillator frequency-to-digital conversion and noise cancellation. ISSCC (2015)
Colin Weltin-Wu, Eythan Familier, Ian Galton
A Linearized Model for the Design of Fractional-N Digital PLLs Based on Dual-Mode Ring Oscillator FDCs. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2015)
Colin Weltin-Wu, Guobi Zhao, Ian Galton
A 3.5 GHz Digital Fractional-N PLL Frequency Synthesizer Based on Ring Oscillator Frequency-to-Digital Conversion. IEEE J. Solid State Circuits 50 (12) (2015)
Colin Weltin-Wu, Yannis P. Tsividis
An Event-driven Clockless Level-Crossing ADC With Signal-Dependent Adaptive Resolution. IEEE J. Solid State Circuits 48 (9) (2013)
Colin Weltin-Wu, Yannis P. Tsividis
An event-driven, alias-free ADC with signal-dependent resolution. VLSIC (2012)
Mariya Kurchuk, Colin Weltin-Wu, Dominique Morche, Yannis P. Tsividis
Event-Driven GHz-Range Continuous-Time Digital Signal Processor With Activity-Dependent Power Dissipation. IEEE J. Solid State Circuits 47 (9) (2012)
Mariya Kurchuk, Colin Weltin-Wu, Dominique Morche, Yannis P. Tsividis
GHz-range continuous-time programmable digital FIR with power dissipation that automatically adapts to signal activity. ISSCC (2011)
Colin Weltin-Wu, Enrico Temporiti, Marco Cusmai, Daniele Baldi, Francesco Svelto
Insights Into Wideband Fractional ADPLLs: Modeling and Calibration of Nonlinearity Induced Fractional Spurs. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2010)
Colin Weltin-Wu, Enrico Temporiti, Daniele Baldi, Marco Cusmai, Francesco Svelto
A 3.5GHz wideband ADPLL with fractional spur suppression through TDC dithering and feedforward compensation. ISSCC (2010)
Enrico Temporiti, Colin Weltin-Wu, Daniele Baldi, Marco Cusmai, Francesco Svelto
A 3.5 GHz Wideband ADPLL With Fractional Spur Suppression Through TDC Dithering and Feedforward Compensation. IEEE J. Solid State Circuits 45 (12) (2010)
Enrico Temporiti, Colin Weltin-Wu, Daniele Baldi, Riccardo Tonietto, Francesco Svelto
Insights into wideband fractional All-Digital PLLs for RF applications. CICC (2009)
Enrico Temporiti, Colin Weltin-Wu, Daniele Baldi, Riccardo Tonietto, Francesco Svelto
A 3 GHz Fractional All-Digital PLL With a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques. IEEE J. Solid State Circuits 44 (3) (2009)
Colin Weltin-Wu, Enrico Temporiti, Daniele Baldi, Francesco Svelto
A 3GHz Fractional-N All-Digital PLL with Precise Time-to-Digital Converter Calibration and Mismatch Correction. ISSCC (2008)