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A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC.

Eric SiragusaIan Galton
Published in: IEEE J. Solid State Circuits (2004)
Keyphrases
  • analog to digital converter
  • random access memory
  • high speed
  • image sensor
  • low cost
  • analog vlsi
  • low power
  • neural network
  • single chip
  • learning algorithm
  • dynamic range
  • delay insensitive