Terri S. Fiez

Publication Activity (10 Years)

Years Active: 1993-2020
Publications (10 Years): 12

Top Venues

IEEE J. Solid State Circuits

CICC

IEEE Trans. Circuits Syst. I Regul. Pap.

VLSIC

Publications

Hamidreza Maghami, Pedram Payandehnia, Hossein Mirzaie, Ramin Zanbaghi, Hossein Zareie, Justin B. Goins, Siladitya Dey, Kartikeya Mayaram, Terri S. Fiez
A Highly Linear OTA-Less 1-1 MASH VCO-Based ΔΣ ADC With an Efficient Phase Quantization Noise Extraction Technique. IEEE J. Solid State Circuits 55 (3) (2020)
Hossein Mirzaie, Hamidreza Maghami, Ramin Zanbaghi, Pedram Payandehnia, Kartikeya Mayaram, Terri S. Fiez
A 72.4-dB SNDR 92-dB SFDR Blocker Tolerant CT $\Delta\Sigma$ Modulator With Inherent DWA. IEEE Trans. Circuits Syst. II Express Briefs (2) (2019)
Hamidreza Maghami, Pedram Payandehnia, Hossein Mirzaie, Ramin Zanbaghi, Siladitya Dey, Kartikeya Mayaram, Terri S. Fiez
A Highly Linear OTA-Free VCO-Based 1-1 MASH $\Delta\Sigma$ ADC. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2019)
Siladitya Dey, Kartikeya Mayaram, Terri S. Fiez
order noise-shaping and pipelined SAR-VCO based quantizer. CICC (2019)
Hamidreza Maghami, Pedram Payandehnia, Hossein Mirzaie, Ramin Zanbaghi, Siladitya Dey, Justin B. Goins, Kartikeya Mayaram, Terri S. Fiez
0.9V, 79.7dB SNDR, 2MHz-BW, Highly linear OTA-less 1-1 MASH VCO-based ΔΣ with a Novel Phase Quantization Noise Extraction Technique. CICC (2019)
Siladitya Dey, Karthikeyan Reddy, Kartikeya Mayaram, Terri S. Fiez
A 50 MHz BW 76.1 dB DR Two-Stage Continuous-Time Delta-Sigma Modulator With VCO Quantizer Nonlinearity Cancellation. IEEE J. Solid State Circuits 53 (3) (2018)
James J. Sluss, Bonnie H. Ferri, Terri S. Fiez, Joseph L. A. Hughes, Rob Reilly, Ali Mehrizi-Sani, Jeffrey E. Froyd, Justin M. Foley, Shanna Daly, Catherine Lenaway, Jamie Phillips, Yu-Tzu Lin, Cheng-Chih Wu, Ting-Yun Hou, Yu-Chih Lin, Fang-Ying Yang, Chia-Hu Chang, Hitoshi Sasaki, Takako Akakura, Gabriel Diaz, Ramon Carrasco, Beth Rieken, Mark Schar, Sheri Sheppard, Stephanie Cutler, Thomas A. Litzinger, Sarah E. Zappe, Michael Alley, Edwin C. Jones
2017 IEEE Education Society Awards, 2017 Frontiers in Education Conference Awards, and Selected IEEE Awards. IEEE Trans. Educ. 61 (1) (2018)
Hamidreza Maghami, Hossein Mirzaie, Pedram Payandehnia, Kartikeya Mayaram, Ramin Zanbaghi, Terri S. Fiez
A Novel Time-Domain Phase Quantization Noise Extraction for a VCO-based Quantizer. MWSCAS (2018)
Hamidreza Maghami, Pedram Payandehnia, Hossein Mirzaie, Kartikeya Mayaram, Ramin Zanbaghi, Terri S. Fiez
A highly linear OTA-free VCO-based 1-1 MASH ΔΣ ADC. ISCAS (2017)
Siladitya Dey, Karthikeyan Reddy, Kartikeya Mayaram, Terri S. Fiez
A 50 MHz BW 73.5 dB SNDR two-stage continuous-time ΔΣ modulator with VCO quantizer nonlinearity cancellation. CICC (2017)
Ankur Guha Roy, Kartikeya Mayaram, Terri S. Fiez
Fast start-up analysis of resonator based oscillators using a power generation method. IET Circuits Devices Syst. 10 (5) (2016)
Justin B. Goins, Ankur Guha Roy, Kartikeya Mayaram, Terri S. Fiez
JetNet: A proposed protocol for reliable packet delivery in low-power IoT applications. WF-IoT (2016)
Samira Zali Asl, James C. Salvia, Ginel C. Hill, Lijun Will Chen, Kimo Joo, Rajkumar Palwai, Niveditha Arumugam, Meghan Phadke, Shouvik Mukherjee, Haechang Lee, Charles Grosjean, Paul M. Hagelin, Sudhakar Pamarti, Terri S. Fiez, Kofi A. A. Makinwa, Aaron Partridge, Vinod Menon
A 3 ppm 1.5 × 0.8 mm 2 1.0 µA 32.768 kHz MEMS-Based Oscillator. IEEE J. Solid State Circuits 50 (1) (2015)
Ankur Guha Roy, Siladitya Dey, Justin B. Goins, Terri S. Fiez, Kartikeya Mayaram
350 mV, 5 GHz Class-D Enhanced Swing Differential and Quadrature VCOs in 65 nm CMOS. IEEE J. Solid State Circuits 50 (8) (2015)
Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma, Terri S. Fiez, Mike Peng Li
Special session 8C: Hot topic: Designers' and test researchers' roles in analog design-for-test. VTS (2014)
Ronghua Ni, Kartikeya Mayaram, Terri S. Fiez
A 915MHz, 6Mb/s, 80pJ/b BFSK receiver with -76dBm sensitivity for high data rate wireless sensor networks. VLSIC (2014)
Samira Zali Asl, Shouvik Mukherjee, Lijun Will Chen, Kimo Joo, Rajkumar Palwai, Niveditha Arumugam, P. Galle, Meghan Phadke, Charles Grosjean, Jim Salvia, Haechang Lee, Sudhakar Pamarti, Terri S. Fiez, Kofi A. A. Makinwa, Aaron Partridge, Vinod Menon
3ppm 1.0μA 32.768kHz MEMS-based oscillator. ISSCC (2014)
Ankur Guha Roy, Siladitya Dey, Justin B. Goins, Kartikeya Mayaram, Terri S. Fiez
A 350 mV, 5 GHz class-D enhanced swing quadrature VCO in 65 nm CMOS with 198.3 dBc/Hz FoM. CICC (2014)
Ramin Zanbaghi, Pavan Kumar Hanumolu, Terri S. Fiez
An 80-dB DR, 7.2-MHz Bandwidth Single Opamp Biquad Based CT ΔΣ Modulator Dissipating 13.7-mW. IEEE J. Solid State Circuits 48 (2) (2013)
Ronghua Ni, Kartikeya Mayaram, Terri S. Fiez
A 2.4 GHz Hybrid Polyphase Filter Based BFSK Receiver With High Frequency Offset Tolerance for Wireless Sensor Networks. IEEE J. Solid State Circuits 48 (5) (2013)
Ramin Zanbaghi, Saurabh Saxena, Gabor C. Temes, Terri S. Fiez
A 75-dB SNDR, 5-MHz Bandwidth Stage-Shared 2-2 MASH ΔΣ Modulator Dissipating 16 mW Power. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2012)
Ronghua Ni, Kartikeya Mayaram, Terri S. Fiez
A 2.4GHz hybrid PPF based BFSK receiver with ±180ppm frequency offset tolerance for wireless sensor networks. VLSIC (2012)
Jim Le, Christopher Hanken, Martin Held, Michael S. Hagedorn, Kartikeya Mayaram, Terri S. Fiez
Experimental Characterization and Analysis of an Asynchronous Approach for Reduction of Substrate Noise in Digital Circuitry. IEEE Trans. Very Large Scale Integr. Syst. 20 (2) (2012)
Samira Zali Asl, Saurabh Saxena, Pavan Kumar Hanumolu, Kartikeya Mayaram, Terri S. Fiez
A 12.5-bit 4 MHz 13.8 mW MASH ΔΣ Modulator With Multirated VCO-Based ADC. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2012)
Pavan Kumar Hanumolu, Un-Ku Moon, Terri S. Fiez
Tutorial T5: Advanced Analog-Mixed Signal System and Circuit Techniques. VLSI Design (2012)
Ramin Zanbaghi, Saurabh Saxena, Gabor C. Temes, Terri S. Fiez
A 75dB SNDR, 10MHz conversion bandwidth stage-shared 2-2 MASH ΔΣ modulator dissipating 9mW. CICC (2011)
Adam C. Heiberg, Thomas William Brown, Terri S. Fiez, Kartikeya Mayaram
A 250 mV, 352 μ W GPS Receiver RF Front-End in 130 nm CMOS. IEEE J. Solid State Circuits 46 (4) (2011)
Thomas William Brown, Farhad Farhabakhshian, Ankur Guha Roy, Terri S. Fiez, Kartikeya Mayaram
A 475 mV, 4.9 GHz Enhanced Swing Differential Colpitts VCO With Phase Noise of -136 dBc/Hz at a 3 MHz Offset Frequency. IEEE J. Solid State Circuits 46 (8) (2011)
Samira Zali Asl, Saurabh Saxena, Pavan Kumar Hanumolu, Kartikeya Mayaram, Terri S. Fiez
A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer. CICC (2011)
Chao Shi, Brian Miller, Kartikeya Mayaram, Terri S. Fiez
A Multiple-Input Boost Converter for Low-Power Energy Harvesting. IEEE Trans. Circuits Syst. II Express Briefs (12) (2011)
Ramin Zanbaghi, Terri S. Fiez, Gabor C. Temes
A new zero-optimization scheme for noise-coupled ΔΣ ADCs. ISCAS (2010)
James Ayers, Kartikeya Mayaram, Terri S. Fiez
An Ultralow-Power Receiver for Wireless Sensor Networks. IEEE J. Solid State Circuits 45 (9) (2010)
Farhad Farhabakhshian, Thomas William Brown, Kartikeya Mayaram, Terri S. Fiez
A 475 mV, 4.9 GHz enhanced swing differential Colpitts VCO in 130 nm CMOS with an FoM of 196.2 dBc/Hz. CICC (2010)
Wai Leng Cheong, Brian E. Owens, Hui En Pham, Christopher Hanken, Jim Le, Terri S. Fiez, Kartikeya Mayaram
Comparison of supply noise and substrate noise reduction in SiGe BiCMOS and FDSOI processes. ISQED (2009)
Ramin Zanbaghi, Terri S. Fiez
A Novel Low Power Hybrid Loop Filter for Continuous-time Sigma-delta Modulators. ISCAS (2009)
Thomas William Brown, Mikko Hakkarainen, Terri S. Fiez
Frequency-Dependent Sampling Linearity. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2009)
Napong Panitantum, Kartikeya Mayaram, Terri S. Fiez
A 900-MHz low-power transmitter with fast frequency calibration for wireless sensor networks. CICC (2008)
Chenggang Xu, Ranjit Gharpurey, Terri S. Fiez, Kartikeya Mayaram
Extraction of Parasitics in Inhomogeneous Substrates With a New Green Function-Based Method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (9) (2008)
Triet Le, Kartikeya Mayaram, Terri S. Fiez
Efficient Far-Field Radio Frequency Energy Harvesting for Passively Powered Sensor Networks. IEEE J. Solid State Circuits 43 (5) (2008)
James Ayers, Kartikeya Mayaram, Terri S. Fiez
A 0.4 nJ/b 900MHz CMOS BFSK super-regenerative receiver. CICC (2008)
Christopher Hanken, Jim Le, Terri S. Fiez, Kartikeya Mayaram
Simulation and Modeling of Substrate Noise Generation from Synchronous and Asynchronous Digital Logic Circuits. CICC (2007)
James Ayers, Kartikeya Mayaram, Terri S. Fiez
Tradeoffs in the Design of CMOS Receivers for Low Power Wireless Sensor Networks. ISCAS (2007)
Brett Peterson, Kartikeya Mayaram, Terri S. Fiez
Automated Extraction of Model Parameters for Noise Coupling Analysis in Silicon Substrates. CICC (2007)
James Ayers, Kartikeya Mayaram, Terri S. Fiez
A Low Power BFSK Super-Regenerative Transceiver. ISCAS (2007)
Zhimin Li, Terri S. Fiez
A 14 Bit Continuous-Time Delta-Sigma A/D Modulator With 2.5 MHz Signal Bandwidth. IEEE J. Solid State Circuits 42 (9) (2007)
Donald Heer, Carlos Jensen, Terri S. Fiez
Finding a Way: What can Computer Science Education Do? FECS (2007)
Jim Le, Christopher Hanken, Martin Held, Michael S. Hagedorn, Kartikeya Mayaram, Terri S. Fiez
Comparison and Impact of Substrate Noise Generated by Clocked and Clockless Digital Circuitry. CICC (2006)
Thomas William Brown, Terri S. Fiez, Mikko Hakkarainen
Prediction and Characterization of Frequency Dependent MOS Switch Linearity and the Design Implications. CICC (2006)
Triet Le, Jifeng Han, Annette R. von Jouanne, Kartikeya Mayaram, Terri S. Fiez
Piezoelectric micro-power generation interface circuits. IEEE J. Solid State Circuits 41 (6) (2006)
Arathi Sundaresan, Terri S. Fiez, Kartikeya Mayaram
Sizing Ground Taps to Minimize Substrate Noise Coupling in RF LNAs. CICC (2006)
Triet Le, Kartikeya Mayaram, Terri S. Fiez
Efficient Far-Field Radio Frequency Power Conversion System for Passively Powered Sensor Networks. CICC (2006)
Scott Hazenboom, Terri S. Fiez, Kartikeya Mayaram
A comparison of substrate noise coupling in lightly and heavily doped CMOS processes for 2.4-GHz LNAs. IEEE J. Solid State Circuits 41 (3) (2006)
Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram
An error control method for application of the discrete cosine transform to extraction of substrate parasitics in ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (5) (2006)
Patrick Birrer, Sasi Kumar Arunachalam, Martin Held, Kartikeya Mayaram, Terri S. Fiez
Schematic-Driven Substrate Noise Coupling Analysis in Mixed-Signal IC Designs. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2006)
Chenggang Xu, Ranjit Gharpurey, Terri S. Fiez, Kartikeya Mayaram
A green function-based parasitic extraction method for inhomogeneous substrate layers. DAC (2005)
Ajit Sharma, Patrick Birrer, Sasi Kumar Arunachalam, Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram
Accurate Prediction of Substrate Parasitics in Heavily Doped CMOS Processes Using a Calibrated Boundary Element Solver. IEEE Trans. Very Large Scale Integr. Syst. 13 (7) (2005)
Brian E. Owens, Sirisha Adluri, Patrick Birrer, Robert Shreeve, Sasi Kumar Arunachalam, Kartikeya Mayaram, Terri S. Fiez
Simulation and measurement of supply and substrate noise in mixed-signal ICs. IEEE J. Solid State Circuits 40 (2) (2005)
Husni M. Habal, Kartikeya Mayaram, Terri S. Fiez
Accurate and efficient simulation of synchronous digital switching noise in systems on a chip. IEEE Trans. Very Large Scale Integr. Syst. 13 (3) (2005)
Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram
On the numerical stability of Green's function for substrate coupling in integrated circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (4) (2005)
Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram
An improved Z-parameter macro model for substrate noise coupling. ISCAS (5) (2004)
Scott Hazenboom, Terri S. Fiez, Kartikeya Mayaram
Digital noise coupling mechanisms in a 2.4 GHz LNA for heavily and lightly doped CMOS substrates. CICC (2004)
Ravindranath Naiknaware, Terri S. Fiez
Process-insensitive low-power design of switched-capacitor integrators. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2004)
Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram
An efficient formulation for substrate parasitic extraction accounting for nonuniform current distribution. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2004)
Steven K. Dunlap, Terri S. Fiez
A noise-shaped switching power supply using a delta-sigma modulator. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2004)
Madhu Chennam, Terri S. Fiez
A 0.35µm current-mode T/H with -81dB THD. ISCAS (1) (2004)
Ruoxin Jiang, Terri S. Fiez
A 14-bit delta-sigma ADC with 8×OSR and 4-MHz conversion bandwidth in a 0.18-μm CMOS process. IEEE J. Solid State Circuits 39 (1) (2004)
Aria Eshraghi, Terri S. Fiez
A comparative analysis of parallel delta-sigma ADC architectures. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2004)
Robert Shreeve, Terri S. Fiez, Kartikeya Mayaram
A physical and analytical model for substrate noise coupling analysis. ISCAS (5) (2004)
Ajit Sharma, Chenggang Xu, Wen Kung Chu, Nishath K. Verghese, Terri S. Fiez, Kartikeya Mayaram
A predictive methodology for accurate substrate parasitic extraction. ISCAS (5) (2004)
Patrick Birrer, Terri S. Fiez, Kartikeya Mayaram
Silencer!: a tool for substrate noise coupling analysis. SoCC (2004)
Sachin Ranganathan, Terri S. Fiez
A variable gain high linearity low power baseband filter for WLAN. ISCAS (1) (2004)
Husni M. Habal, Terri S. Fiez, Kartikeya Mayaram
An accurate and efficient estimation of switching noise in synchronous digital circuits. ISCAS (2) (2004)
Roger L. Traylor, Donald Heer, Terri S. Fiez
Using an integrated platform for learning™ to reinvent engineering education. IEEE Trans. Educ. 46 (4) (2003)
Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram
Coupled Simulation of Circuit and Piezoelectric Laminates. ISQED (2003)
Triet Le, Jifeng Han, Annette R. von Jouanne, Kartikeya Mayaram, Terri S. Fiez
Piezoelectric power generation interface circuits. CICC (2003)
Aria Eshraghi, Terri S. Fiez
A time-interleaved parallel /ΔΣ A/D converter. IEEE Trans. Circuits Syst. II Express Briefs 50 (3) (2003)
Brian E. Owens, Patrick Birrer, Sirisha Adluri, Robert Shreeve, Sasi Kumar Arunachalam, Husni Habal, Shu-Ching Hsu, Ajit Sharma, Kartikeya Mayaram, Terri S. Fiez
Strategies for simulation, measurement and suppression of digital noise in mixed-signal circuits. CICC (2003)
Donald Heer, Roger L. Traylor, Tom Thompson, Terri S. Fiez
Enhancing the freshman and sophomore ECE student experience using a platform for learning™. IEEE Trans. Educ. 46 (4) (2003)
R. Batten, Terri S. Fiez
An efficient parallel delta-sigma ADC utilizing a shared multi-bit quantizer. ISCAS (3) (2002)
Nathen Barton, Dicle Özis, Terri S. Fiez, Kartikeya Mayaram
Analysis of jitter in ring oscillators due to deterministic noise. ISCAS (4) (2002)
Zhimin Li, Terri S. Fiez
Dynamic element matching in low oversampling delta sigma ADCs. ISCAS (4) (2002)
Dicle Ozis, Kartikeya Mayaram, Terri S. Fiez
An efficient modeling approach for substrate noise coupling analysis. ISCAS (5) (2002)
Dicle Ozis, Terri S. Fiez, Kartikeya Mayaram
A comprehensive geometry-dependent macromodel for substrate noise coupling in heavily doped CMOS processes. CICC (2002)
Uma Chilakapati, Terri S. Fiez, Aria Eshraghi
A CMOS transconductor with 80-dB SFDR up to 10 MHz. IEEE J. Solid State Circuits 37 (3) (2002)
Nathen Barton, Dicle Ozis, Terri S. Fiez, Kartikeya Mayaram
The effect of supply and substrate noise on jitter in ring oscillators. CICC (2002)
Uma Chilakapati, Terri S. Fiez, Aria Eshraghi
A 3.3 V transconductor in 0.35 μm CMOS with 80 dB SFDR up to 10 MHz. CICC (2001)
Ravindranath Naiknaware, Terri S. Fiez
142 dB ΔΣ ADC with a 100 nV LSB in a 3 V CMOS process. CICC (2000)
Russell E. Radke, Aria Eshraghi, Terri S. Fiez
A 14-bit current-mode ΣΔ DAC based upon rotated data weighted averaging. IEEE J. Solid State Circuits 35 (8) (2000)
Anil Samavedam, Aline Sadate, Kartikeya Mayaram, Terri S. Fiez
A scalable substrate noise coupling model for design of mixed-signal IC's. IEEE J. Solid State Circuits 35 (6) (2000)
Anil Samavedam, Kartikeya Mayaram, Terri S. Fiez
Design-oriented substrate noise coupling macromodels for heavily doped CMOS processes. ISCAS (6) (1999)
Ravindranath Naiknaware, Terri S. Fiez
Automated Hierarchical Cmos Analog Circuit Stack Generation with Intramodule Connectivity and Matching Considerations. IEEE J. Solid State Circuits 34 (3) (1999)
Ravindranath Naiknaware, Terri S. Fiez
Time-referenced single-path multi-bit Sigma-Delta ADC using a VCO based quantizer. ISCAS (2) (1999)
Anil Samavedam, Kartikeya Mayaram, Terri S. Fiez
A scalable substrate noise coupling model for mixed-signal ICs. ICCAD (1999)
Ravindranath Naiknaware, Terri S. Fiez
Switched-capacitor integrator design optimizing for power and process variations. ISCAS (2) (1999)
Russell E. Radke, Aria Eshraghi, Terri S. Fiez
A spurious-free delta-sigma DAC using rotated data weighted averaging. CICC (1999)
Ravindranath Naiknaware, Terri S. Fiez
Automated hierarchical CMOS analog circuit stack generation with intramodule connectivity and matching considerations. IEEE J. Solid State Circuits 34 (3) (1999)
Ravindranath Naiknaware, Terri S. Fiez
Schematic driven module generation for analog circuits with performance optimization and matching considerations. CICC (1998)
Ravindranath Naiknaware, Terri S. Fiez
CMOS analog circuit stack generation with matching constraints. ICCAD (1998)
Eric T. King, Aria Eshraghi, Ian Galton, Terri S. Fiez
A Nyquist-rate delta-sigma A/D converter. IEEE J. Solid State Circuits 33 (1) (1998)
Detlev Schmitt, Terri S. Fiez
A low voltage CMOS current source. ISLPED (1997)

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Publication Activity (10 Years)

Top Topics

Top Venues

Terri S. Fiez