Siladitya Dey

Publication Activity (10 Years)

Years Active: 2014-2021
Publications (10 Years): 8

Top Topics

Iterative Learning Control

Quantization Noise

Clock Frequency

Top Venues

IEEE J. Solid State Circuits

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Yanchao Wang, Siladitya Dey, Tao He, Lukang Shi, Jiawei Zheng, Manjunath Kareppagoudr, Yi Zhang, Kazuki Sobue, Koichi Hamashita, Koji Tomioka, Gabor C. Temes
A Hybrid Continuous Time Incremental and SAR Two-Step ADC with 90.5dB DR over 1MHz BW. A-SSCC (2021)
Hamidreza Maghami, Pedram Payandehnia, Hossein Mirzaie, Ramin Zanbaghi, Hossein Zareie, Justin B. Goins, Siladitya Dey, Kartikeya Mayaram, Terri S. Fiez
A Highly Linear OTA-Less 1-1 MASH VCO-Based ΔΣ ADC With an Efficient Phase Quantization Noise Extraction Technique. IEEE J. Solid State Circuits 55 (3) (2020)
Hamidreza Maghami, Pedram Payandehnia, Hossein Mirzaie, Ramin Zanbaghi, Siladitya Dey, Kartikeya Mayaram, Terri S. Fiez
A Highly Linear OTA-Free VCO-Based 1-1 MASH $\Delta\Sigma$ ADC. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2019)
Siladitya Dey, Kartikeya Mayaram, Terri S. Fiez
order noise-shaping and pipelined SAR-VCO based quantizer. CICC (2019)
Hamidreza Maghami, Pedram Payandehnia, Hossein Mirzaie, Ramin Zanbaghi, Siladitya Dey, Justin B. Goins, Kartikeya Mayaram, Terri S. Fiez
0.9V, 79.7dB SNDR, 2MHz-BW, Highly linear OTA-less 1-1 MASH VCO-based ΔΣ with a Novel Phase Quantization Noise Extraction Technique. CICC (2019)
Siladitya Dey, Karthikeyan Reddy, Kartikeya Mayaram, Terri S. Fiez
A 50 MHz BW 76.1 dB DR Two-Stage Continuous-Time Delta-Sigma Modulator With VCO Quantizer Nonlinearity Cancellation. IEEE J. Solid State Circuits 53 (3) (2018)
Pedram Payandehnia, Hamidreza Maghami, Hossein Mirzaie, Manjunath Kareppagoudr, Siladitya Dey, Massoud Tohidian, Gabor C. Temes
A 0.49-13.3 MHz Tunable Fourth-Order LPF with Complex Poles Achieving 28.7 dBm OIP3. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2018)
Siladitya Dey, Karthikeyan Reddy, Kartikeya Mayaram, Terri S. Fiez
A 50 MHz BW 73.5 dB SNDR two-stage continuous-time ΔΣ modulator with VCO quantizer nonlinearity cancellation. CICC (2017)
Karthikeyan Reddy, Siladitya Dey, Sachin Rao, Brian Young, Praveen Prabha, Pavan Kumar Hanumolu
A 54mW 1.2GS/s 71.5dB SNDR 50MHz BW VCO-based CT ΔΣ ADC using dual phase/frequency feedback in 65nm CMOS. VLSIC (2015)
Ankur Guha Roy, Siladitya Dey, Justin B. Goins, Terri S. Fiez, Kartikeya Mayaram
350 mV, 5 GHz Class-D Enhanced Swing Differential and Quadrature VCOs in 65 nm CMOS. IEEE J. Solid State Circuits 50 (8) (2015)
Ankur Guha Roy, Siladitya Dey, Justin B. Goins, Kartikeya Mayaram, Terri S. Fiez
A 350 mV, 5 GHz class-D enhanced swing quadrature VCO in 65 nm CMOS with 198.3 dBc/Hz FoM. CICC (2014)