Ramin Zanbaghi

Publication Activity (10 Years)

Years Active: 2006-2020
Publications (10 Years): 6

Top Topics

Quantization Noise

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE J. Solid State Circuits

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Hamidreza Maghami, Pedram Payandehnia, Hossein Mirzaie, Ramin Zanbaghi, Hossein Zareie, Justin B. Goins, Siladitya Dey, Kartikeya Mayaram, Terri S. Fiez
A Highly Linear OTA-Less 1-1 MASH VCO-Based ΔΣ ADC With an Efficient Phase Quantization Noise Extraction Technique. IEEE J. Solid State Circuits 55 (3) (2020)
Hossein Mirzaie, Hamidreza Maghami, Ramin Zanbaghi, Pedram Payandehnia, Kartikeya Mayaram, Terri S. Fiez
A 72.4-dB SNDR 92-dB SFDR Blocker Tolerant CT $\Delta\Sigma$ Modulator With Inherent DWA. IEEE Trans. Circuits Syst. II Express Briefs (2) (2019)
Hamidreza Maghami, Pedram Payandehnia, Hossein Mirzaie, Ramin Zanbaghi, Siladitya Dey, Kartikeya Mayaram, Terri S. Fiez
A Highly Linear OTA-Free VCO-Based 1-1 MASH $\Delta\Sigma$ ADC. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2019)
Hamidreza Maghami, Pedram Payandehnia, Hossein Mirzaie, Ramin Zanbaghi, Siladitya Dey, Justin B. Goins, Kartikeya Mayaram, Terri S. Fiez
0.9V, 79.7dB SNDR, 2MHz-BW, Highly linear OTA-less 1-1 MASH VCO-based ΔΣ with a Novel Phase Quantization Noise Extraction Technique. CICC (2019)
Hamidreza Maghami, Hossein Mirzaie, Pedram Payandehnia, Kartikeya Mayaram, Ramin Zanbaghi, Terri S. Fiez
A Novel Time-Domain Phase Quantization Noise Extraction for a VCO-based Quantizer. MWSCAS (2018)
Hamidreza Maghami, Pedram Payandehnia, Hossein Mirzaie, Kartikeya Mayaram, Ramin Zanbaghi, Terri S. Fiez
A highly linear OTA-free VCO-based 1-1 MASH ΔΣ ADC. ISCAS (2017)
Ramin Zanbaghi, Pavan Kumar Hanumolu, Terri S. Fiez
An 80-dB DR, 7.2-MHz Bandwidth Single Opamp Biquad Based CT ΔΣ Modulator Dissipating 13.7-mW. IEEE J. Solid State Circuits 48 (2) (2013)
Ramin Zanbaghi, Saurabh Saxena, Gabor C. Temes, Terri S. Fiez
A 75-dB SNDR, 5-MHz Bandwidth Stage-Shared 2-2 MASH ΔΣ Modulator Dissipating 16 mW Power. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2012)
Ramin Zanbaghi, Saurabh Saxena, Gabor C. Temes, Terri S. Fiez
A 75dB SNDR, 10MHz conversion bandwidth stage-shared 2-2 MASH ΔΣ modulator dissipating 9mW. CICC (2011)
Ramin Zanbaghi, Terri S. Fiez, Gabor C. Temes
A new zero-optimization scheme for noise-coupled ΔΣ ADCs. ISCAS (2010)
Ramin Zanbaghi, Terri S. Fiez
A Novel Low Power Hybrid Loop Filter for Continuous-time Sigma-delta Modulators. ISCAS (2009)
Ramin Zanbaghi, Seyed Mojtaba Atarodi, Armin Tajalli
A Power Optimized Base-Band Circuitry for the Low-IF Receivers. ISCAS (2007)
Mohsen Moezzi, Ramin Zanbaghi, Mojtaba Atarodi, Armin Tajalli
A Q-Enhanced Biquadratic Gm-C Filter for High Frequency Applications. ICECS (2006)