Saurabh Saxena

Publication Activity (10 Years)

Years Active: 2009-2024
Publications (10 Years): 50

Top Topics

Language Modeling Framework

Phase Modulation

Diffusion Models

Top Venues

IEEE J. Solid State Circuits

Publications

Daniel Watson, Saurabh Saxena, Lala Li, Andrea Tagliasacchi, David J. Fleet
Controlling Space and Time with Diffusion Models. CoRR (2024)
Ethan Weber, Aleksander Holynski, Varun Jampani, Saurabh Saxena, Noah Snavely, Abhishek Kar, Angjoo Kanazawa
NeRFiller: Completing Scenes via Generative 3D Inpainting. CoRR (2023)
Snigdha Jakkoju, Deepthi J. Bandarupalli, Anil Srikanth, Saji Thomas, Saurabh Saxena
A 2.25 GHz PLL with 0.05-2 MHz Inloop Phase Modulation and -70 dBc Reference Spur for Telemetry Applications. VLSID (2023)
Shivam Nigam, Mukund Murali, Hari Shanker Gupta, Saurabh Saxena
A 105-525MHz Integer-N Phase-Locked Loop in Indigenous SCL 180nm CMOS. VLSID (2023)
Saurabh Saxena, Abhishek Kar, Mohammad Norouzi, David J. Fleet
Monocular Depth Estimation using Diffusion Models. CoRR (2023)
Saurabh Saxena, Junhwa Hur, Charles Herrmann, Deqing Sun, David J. Fleet
Zero-Shot Metric Depth with a Field-of-View Conditioned Diffusion Model. CoRR (2023)
Saurabh Saxena, Charles Herrmann, Junhwa Hur, Abhishek Kar, Mohammad Norouzi, Deqing Sun, David J. Fleet
The Surprising Effectiveness of Diffusion Models for Optical Flow and Monocular Depth Estimation. CoRR (2023)
Saurabh Saxena, Charles Herrmann, Junhwa Hur, Abhishek Kar, Mohammad Norouzi, Deqing Sun, David J. Fleet
The Surprising Effectiveness of Diffusion Models for Optical Flow and Monocular Depth Estimation. NeurIPS (2023)
Jaya Deepthi Bandarupalli, Saurabh Saxena
A 0.49-9.8 Gb/s 0.1-1V Output Swing Transmitter with 38.4MHz Reference and <30 ns Turn-On Time. ESSCIRC (2023)
Ting Chen, Lala Li, Saurabh Saxena, Geoffrey E. Hinton, David J. Fleet
A Generalist Framework for Panoptic Segmentation of Images and Videos. ICCV (2023)
Sonam Sadhukhan, Pranav Kumar, Arpan Thakkar, Apoorva Bhatia, Saurabh Saxena
A Class-C Injection-Locked Tripler with 48 dB Sub-Harmonic Suppression and 15 fs Additive RMS Jitter in 0.13μm BiCMOS Process. ISCAS (2022)
Chitwan Saharia, William Chan, Saurabh Saxena, Lala Li, Jay Whang, Emily Denton, Seyed Kamyar Seyed Ghasemipour, Burcu Karagol Ayan, S. Sara Mahdavi, Rapha Gontijo Lopes, Tim Salimans, Jonathan Ho, David J. Fleet, Mohammad Norouzi
Photorealistic Text-to-Image Diffusion Models with Deep Language Understanding. CoRR (2022)
Saurabh Saxena, Neda Yaghoobian
A Surface Energy Balance Model for Predicting Temperature Evolution of Random-Shaped Smoldering Objects in Open Environments. CoRR (2022)
Ting Chen, Saurabh Saxena, Lala Li, David J. Fleet, Geoffrey E. Hinton
Pix2seq: A Language Modeling Framework for Object Detection. ICLR (2022)
Jaya Deepthi Bandarupalli, Saurabh Saxena
Jitter and 0.98-1.06 mW/GHz in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 69 (9) (2022)
R. Gautam, Saurabh Saxena
A 1.12-1.91 mW/GHz 2.46-4.92 GHz Cascaded Clock Multiplier in 65 nm CMOS. IEEE J. Solid State Circuits 57 (6) (2022)
Shraman Mukherjee, Sumantra Seth, Saurabh Saxena
A 5-Gb/s PAM4 Voltage Mode Transmitter with Current Mode Continuous Time Linear Equalizer. VLSID (2022)
Ting Chen, Lala Li, Saurabh Saxena, Geoffrey E. Hinton, David J. Fleet
A Generalist Framework for Panoptic Segmentation of Images and Videos. CoRR (2022)
Ting Chen, Saurabh Saxena, Lala Li, Tsung-Yi Lin, David J. Fleet, Geoffrey E. Hinton
A Unified Sequence Interface for Vision Tasks. CoRR (2022)
Ting Chen, Saurabh Saxena, Lala Li, Tsung-Yi Lin, David J. Fleet, Geoffrey E. Hinton
A Unified Sequence Interface for Vision Tasks. NeurIPS (2022)
Chitwan Saharia, William Chan, Saurabh Saxena, Lala Li, Jay Whang, Emily L. Denton, Seyed Kamyar Seyed Ghasemipour, Raphael Gontijo Lopes, Burcu Karagol Ayan, Tim Salimans, Jonathan Ho, David J. Fleet, Mohammad Norouzi
Photorealistic Text-to-Image Diffusion Models with Deep Language Understanding. NeurIPS (2022)
Darius Roman, Saurabh Saxena, Jens Bruns, Valentin Robu, Michael G. Pecht, David Flynn
A Machine Learning Degradation Model for Electrochemical Capacitors Operated at High Temperature. IEEE Access 9 (2021)
Ting Chen, Saurabh Saxena, Lala Li, David J. Fleet, Geoffrey E. Hinton
Pix2seq: A Language Modeling Framework for Object Detection. CoRR (2021)
Darius Roman, Saurabh Saxena, Valentin Robu, Michael G. Pecht, David Flynn
Machine learning pipeline for battery state-of-health estimation. Nat. Mach. Intell. 3 (5) (2021)
Darius Roman, Saurabh Saxena, Valentin Robu, Michael G. Pecht, David Flynn
Machine learning pipeline for battery state of health estimation. CoRR (2021)
Chitwan Saharia, William Chan, Saurabh Saxena, Mohammad Norouzi
Non-Autoregressive Machine Translation with Latent Alignments. EMNLP (1) (2020)
Chitwan Saharia, William Chan, Saurabh Saxena, Mohammad Norouzi
Non-Autoregressive Machine Translation with Latent Alignments. CoRR (2020)
R. Gautam, Jaya Deepthi Bandarupalli, Saurabh Saxena
A 2.5-5GHz Injection-Locked Clock Multiplier with Embedded Phase Interpolator in 65nm CMOS. ISCAS (2020)
Weiping Diao, Saurabh Saxena, Michael G. Pecht
Analysis of Specified Capacity in Power Banks. IEEE Access 8 (2020)
Shraman Mukherjee, Ashish Das, Sumantra Seth, Saurabh Saxena
An Energy-Efficient 3Gb/s PAM4 Full-Duplex Transmitter With 2-Tap Feed Forward Equalizer. IEEE Trans. Circuits Syst. II Express Briefs (5) (2020)
Xingyan Yao, Saurabh Saxena, Lei Su, Michael G. Pecht
The Explosive Nature of Tab Burrs in Li-Ion Batteries. IEEE Access 7 (2019)
Saikath Bhattacharya, Lance Fiondella, Saurabh Saxena, Michael G. Pecht
Quantifying the Impact of Prognostic Distance on Average Cost per Cycle. ICPHM (2019)
Saurabh Saxena, Myeongsu Kang, Yinjiao Xing, Michael G. Pecht
Anomaly Detection During Lithium-ion Battery Qualification Testing. ICPHM (2018)
Saurabh Saxena, Lingxi Kong, Michael G. Pecht
Exploding E-Cigarettes: A Battery Safety Issue. IEEE Access 6 (2018)
Qadeer A. Khan, Saurabh Saxena, Abirmoya Santra
Area and Current Efficient Capacitor-Less Low Drop-Out Regulator Using Time-Based Error Amplifier. ISCAS (2018)
Ahmed Elkholy, Saurabh Saxena, Guanghua Shu, Amr Elshazly, Pavan Kumar Hanumolu
Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers. IEEE J. Solid State Circuits 53 (6) (2018)
Esteban Real, Sherry Moore, Andrew Selle, Saurabh Saxena, Yutaka Leon Suematsu, Jie Tan, Quoc V. Le, Alexey Kurakin
Large-Scale Evolution of Image Classifiers. ICML (2017)
Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Romesh Kumar Nandwana, Saurabh Saxena, Brian Young, Woo-Seok Choi, Pavan Kumar Hanumolu
A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS. IEEE J. Solid State Circuits 52 (9) (2017)
Saurabh Saxena, Guanghua Shu, Romesh Kumar Nandwana, Mrunmay Talegaonkar, Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, Pavan Kumar Hanumolu
A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver. IEEE J. Solid State Circuits 52 (5) (2017)
Esteban Real, Sherry Moore, Andrew Selle, Saurabh Saxena, Yutaka Leon Suematsu, Quoc V. Le, Alex Kurakin
Large-Scale Evolution of Image Classifiers. CoRR (2017)
Romesh Kumar Nandwana, Saurabh Saxena, Ahmed Elkholy, Mrunmay Talegaonkar, Junheng Zhu, Woo-Seok Choi, Ahmed Elmallah, Pavan Kumar Hanumolu
29.6 A 3-to-10Gb/s 5.75pJ/b transceiver with flexible clocking in 65nm CMOS. ISSCC (2017)
Romesh Kumar Nandwana, Saurabh Saxena, Amr Elshazly, Kartikeya Mayaram, Pavan Kumar Hanumolu
A 1-to-2048 Fully-Integrated Cascaded Digital Frequency Synthesizer for Low Frequency Reference Clocks Using Scrambling TDC. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2017)
Ahmed Elkholy, Saurabh Saxena, Romesh Kumar Nandwana, Amr Elshazly, Pavan Kumar Hanumolu
A 2.0-5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider. IEEE J. Solid State Circuits 51 (8) (2016)
Guanghua Shu, Woo-Seok Choi, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Romesh Kumar Nandwana, Ahmed Elkholy, Da Wei, Timir Nandi, Pavan Kumar Hanumolu
23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS. ISSCC (2016)
Guanghua Shu, Woo-Seok Choi, Saurabh Saxena, Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Pavan Kumar Hanumolu
A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition. IEEE J. Solid State Circuits 51 (2) (2016)
Ahmed Elkholy, Saurabh Saxena, Romesh Kumar Nandwana, Amr Elshazly, Pavan Kumar Hanumolu
A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9psrms integrated-jitter. CICC (2015)
Romesh Kumar Nandwana, Tejasvi Anand, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Ahmed Elkholy, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu
A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method. IEEE J. Solid State Circuits 50 (4) (2015)
Tejasvi Anand, Mrunmay Talegaonkar, Ahmed Elkholy, Saurabh Saxena, Amr Elshazly, Pavan Kumar Hanumolu
A 7 Gb/s Embedded Clock Transceiver for Energy Proportional Links. IEEE J. Solid State Circuits 50 (12) (2015)
Tejasvi Anand, Mrunmay Talegaonkar, Ahmed Elkholy, Saurabh Saxena, Amr Elshazly, Pavan Kumar Hanumolu
3.7 A 7Gb/s rapid on/off embedded-clock serial-link transceiver with 20ns power-on time, 740μW off-state power for energy-proportional links in 65nm CMOS. ISSCC (2015)
Saurabh Saxena, Guanghua Shu, Romesh Kumar Nandwana, Mrunmay Talegaonkar, Ahmed Elkholy, Tejasvi Anand, Seong Joong Kim, Woo-Seok Choi, Pavan Kumar Hanumolu
A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS. VLSIC (2015)
Guanghua Shu, Saurabh Saxena, Woo-Seok Choi, Mrunmay Talegaonkar, Rajesh Inti, Amr Elshazly, Brian Young, Pavan Kumar Hanumolu
A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop. IEEE J. Solid State Circuits 49 (4) (2014)
Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Romesh Kumar Nandwana, Saurabh Saxena, Brian Young, Woo-Seok Choi, Pavan Kumar Hanumolu
A 4.4-5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter. VLSIC (2014)
Ahmed Elkholy, Amr Elshazly, Saurabh Saxena, Guanghua Shu, Pavan Kumar Hanumolu
15.4 A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS. ISSCC (2014)
Saurabh Saxena, Romesh Kumar Nandwana, Pavan Kumar Hanumolu
A 5 Gb/s Energy-Efficient Voltage-Mode Transmitter Using Time-Based De-Emphasis. IEEE J. Solid State Circuits 49 (8) (2014)
Guanghua Shu, Woo-Seok Choi, Saurabh Saxena, Tejasvi Anand, Amr Elshazly, Pavan Kumar Hanumolu
8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS. ISSCC (2014)
Romesh Kumar Nandwana, Tejasvi Anand, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Ahmed Elkholy, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu
A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement. VLSIC (2014)
Saurabh Saxena, Romesh Kumar Nandwana, Pavan Kumar Hanumolu
A 5 Gb/s 3.2 mW/Gb/s 28 dB loss-compensating pulse-width modulated voltage-mode transmitter. CICC (2013)
Ramin Zanbaghi, Saurabh Saxena, Gabor C. Temes, Terri S. Fiez
A 75-dB SNDR, 5-MHz Bandwidth Stage-Shared 2-2 MASH ΔΣ Modulator Dissipating 16 mW Power. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2012)
Samira Zali Asl, Saurabh Saxena, Pavan Kumar Hanumolu, Kartikeya Mayaram, Terri S. Fiez
A 12.5-bit 4 MHz 13.8 mW MASH ΔΣ Modulator With Multirated VCO-Based ADC. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2012)
Ramin Zanbaghi, Saurabh Saxena, Gabor C. Temes, Terri S. Fiez
A 75dB SNDR, 10MHz conversion bandwidth stage-shared 2-2 MASH ΔΣ modulator dissipating 9mW. CICC (2011)
Samira Zali Asl, Saurabh Saxena, Pavan Kumar Hanumolu, Kartikeya Mayaram, Terri S. Fiez
A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer. CICC (2011)
Saurabh Saxena, Jin Jang
Rapid-Thermal Annealing of Amorphous Silicon on Oxide Semiconductors. IEICE Trans. Electron. (10) (2010)
Saurabh Saxena, Prabu Sankar, Shanthi Pavan
Automatic Tuning of Time Constants in Single Bit Continuous-time Delta-sigma Modulators. ISCAS (2009)