Kartikeya Mayaram

ORCID

Publication Activity (10 Years)

Years Active: 1986-2020
Publications (10 Years): 12

Top Venues

CICC

IEEE J. Solid State Circuits

IEEE Trans. Circuits Syst. I Regul. Pap.

VLSIC

Publications

Hamidreza Maghami, Pedram Payandehnia, Hossein Mirzaie, Ramin Zanbaghi, Hossein Zareie, Justin B. Goins, Siladitya Dey, Kartikeya Mayaram, Terri S. Fiez
A Highly Linear OTA-Less 1-1 MASH VCO-Based ΔΣ ADC With an Efficient Phase Quantization Noise Extraction Technique. IEEE J. Solid State Circuits 55 (3) (2020)
Hossein Mirzaie, Hamidreza Maghami, Ramin Zanbaghi, Pedram Payandehnia, Kartikeya Mayaram, Terri S. Fiez
A 72.4-dB SNDR 92-dB SFDR Blocker Tolerant CT $\Delta\Sigma$ Modulator With Inherent DWA. IEEE Trans. Circuits Syst. II Express Briefs (2) (2019)
Hamidreza Maghami, Pedram Payandehnia, Hossein Mirzaie, Ramin Zanbaghi, Siladitya Dey, Kartikeya Mayaram, Terri S. Fiez
A Highly Linear OTA-Free VCO-Based 1-1 MASH $\Delta\Sigma$ ADC. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2019)
Siladitya Dey, Kartikeya Mayaram, Terri S. Fiez
order noise-shaping and pipelined SAR-VCO based quantizer. CICC (2019)
Hamidreza Maghami, Pedram Payandehnia, Hossein Mirzaie, Ramin Zanbaghi, Siladitya Dey, Justin B. Goins, Kartikeya Mayaram, Terri S. Fiez
0.9V, 79.7dB SNDR, 2MHz-BW, Highly linear OTA-less 1-1 MASH VCO-based ΔΣ with a Novel Phase Quantization Noise Extraction Technique. CICC (2019)
Siladitya Dey, Karthikeyan Reddy, Kartikeya Mayaram, Terri S. Fiez
A 50 MHz BW 76.1 dB DR Two-Stage Continuous-Time Delta-Sigma Modulator With VCO Quantizer Nonlinearity Cancellation. IEEE J. Solid State Circuits 53 (3) (2018)
Hamidreza Maghami, Hossein Mirzaie, Pedram Payandehnia, Kartikeya Mayaram, Ramin Zanbaghi, Terri S. Fiez
A Novel Time-Domain Phase Quantization Noise Extraction for a VCO-based Quantizer. MWSCAS (2018)
Hamidreza Maghami, Pedram Payandehnia, Hossein Mirzaie, Kartikeya Mayaram, Ramin Zanbaghi, Terri S. Fiez
A highly linear OTA-free VCO-based 1-1 MASH ΔΣ ADC. ISCAS (2017)
Romesh Kumar Nandwana, Saurabh Saxena, Amr Elshazly, Kartikeya Mayaram, Pavan Kumar Hanumolu
A 1-to-2048 Fully-Integrated Cascaded Digital Frequency Synthesizer for Low Frequency Reference Clocks Using Scrambling TDC. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2017)
Siladitya Dey, Karthikeyan Reddy, Kartikeya Mayaram, Terri S. Fiez
A 50 MHz BW 73.5 dB SNDR two-stage continuous-time ΔΣ modulator with VCO quantizer nonlinearity cancellation. CICC (2017)
Ankur Guha Roy, Kartikeya Mayaram, Terri S. Fiez
Fast start-up analysis of resonator based oscillators using a power generation method. IET Circuits Devices Syst. 10 (5) (2016)
Justin B. Goins, Ankur Guha Roy, Kartikeya Mayaram, Terri S. Fiez
JetNet: A proposed protocol for reliable packet delivery in low-power IoT applications. WF-IoT (2016)
Ankur Guha Roy, Siladitya Dey, Justin B. Goins, Terri S. Fiez, Kartikeya Mayaram
350 mV, 5 GHz Class-D Enhanced Swing Differential and Quadrature VCOs in 65 nm CMOS. IEEE J. Solid State Circuits 50 (8) (2015)
Ronghua Ni, Kartikeya Mayaram, Terri S. Fiez
A 915MHz, 6Mb/s, 80pJ/b BFSK receiver with -76dBm sensitivity for high data rate wireless sensor networks. VLSIC (2014)
Ankur Guha Roy, Siladitya Dey, Justin B. Goins, Kartikeya Mayaram, Terri S. Fiez
A 350 mV, 5 GHz class-D enhanced swing quadrature VCO in 65 nm CMOS with 198.3 dBc/Hz FoM. CICC (2014)
Ronghua Ni, Kartikeya Mayaram, Terri S. Fiez
A 2.4 GHz Hybrid Polyphase Filter Based BFSK Receiver With High Frequency Offset Tolerance for Wireless Sensor Networks. IEEE J. Solid State Circuits 48 (5) (2013)
Ronghua Ni, Kartikeya Mayaram, Terri S. Fiez
A 2.4GHz hybrid PPF based BFSK receiver with ±180ppm frequency offset tolerance for wireless sensor networks. VLSIC (2012)
Jim Le, Christopher Hanken, Martin Held, Michael S. Hagedorn, Kartikeya Mayaram, Terri S. Fiez
Experimental Characterization and Analysis of an Asynchronous Approach for Reduction of Substrate Noise in Digital Circuitry. IEEE Trans. Very Large Scale Integr. Syst. 20 (2) (2012)
Samira Zali Asl, Saurabh Saxena, Pavan Kumar Hanumolu, Kartikeya Mayaram, Terri S. Fiez
A 12.5-bit 4 MHz 13.8 mW MASH ΔΣ Modulator With Multirated VCO-Based ADC. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2012)
Adam C. Heiberg, Thomas William Brown, Terri S. Fiez, Kartikeya Mayaram
A 250 mV, 352 μ W GPS Receiver RF Front-End in 130 nm CMOS. IEEE J. Solid State Circuits 46 (4) (2011)
Igor Vytyaz, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram
Design-Oriented Analysis of Circuits With Equality Constraints. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2011)
Thomas William Brown, Farhad Farhabakhshian, Ankur Guha Roy, Terri S. Fiez, Kartikeya Mayaram
A 475 mV, 4.9 GHz Enhanced Swing Differential Colpitts VCO With Phase Noise of -136 dBc/Hz at a 3 MHz Offset Frequency. IEEE J. Solid State Circuits 46 (8) (2011)
Samira Zali Asl, Saurabh Saxena, Pavan Kumar Hanumolu, Kartikeya Mayaram, Terri S. Fiez
A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer. CICC (2011)
Chao Shi, Brian Miller, Kartikeya Mayaram, Terri S. Fiez
A Multiple-Input Boost Converter for Low-Power Energy Harvesting. IEEE Trans. Circuits Syst. II Express Briefs (12) (2011)
James Ayers, Kartikeya Mayaram, Terri S. Fiez
An Ultralow-Power Receiver for Wireless Sensor Networks. IEEE J. Solid State Circuits 45 (9) (2010)
Farhad Farhabakhshian, Thomas William Brown, Kartikeya Mayaram, Terri S. Fiez
A 475 mV, 4.9 GHz enhanced swing differential Colpitts VCO in 130 nm CMOS with an FoM of 196.2 dBc/Hz. CICC (2010)
Volodymyr Kratyuk, Pavan Kumar Hanumolu, Kerem Ok, Un-Ku Moon, Kartikeya Mayaram
A Digital PLL With a Stochastic Time-to-Digital Converter. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2009)
Wai Leng Cheong, Brian E. Owens, Hui En Pham, Christopher Hanken, Jim Le, Terri S. Fiez, Kartikeya Mayaram
Comparison of supply noise and substrate noise reduction in SiGe BiCMOS and FDSOI processes. ISQED (2009)
Igor Vytyaz, David C. Lee, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram
Automated Design and Optimization of Low-Noise Oscillators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (5) (2009)
Ting Wu, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon
Method for a Constant Loop Bandwidth in LC-VCO PLL Frequency Synthesizers. IEEE J. Solid State Circuits 44 (2) (2009)
Igor Vytyaz, David C. Lee, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram
Sensitivity Analysis for Oscillators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (9) (2008)
Igor Vytyaz, Josh Carnes, Ting Wu, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram
Noise tolerant oscillator design using perturbation projection vector analysis. CICC (2008)
Napong Panitantum, Kartikeya Mayaram, Terri S. Fiez
A 900-MHz low-power transmitter with fast frequency calibration for wireless sensor networks. CICC (2008)
Igor Vytyaz, David C. Lee, Un-Ku Moon, Kartikeya Mayaram
Parameter variation analysis for voltage controlled oscillators in phase-locked loops. ISCAS (2008)
Igor Vytyaz, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram
Periodic Steady-State Analysis Augmented with Design Equality Constraints. DATE (2008)
Chenggang Xu, Ranjit Gharpurey, Terri S. Fiez, Kartikeya Mayaram
Extraction of Parasitics in Inhomogeneous Substrates With a New Green Function-Based Method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (9) (2008)
Triet Le, Kartikeya Mayaram, Terri S. Fiez
Efficient Far-Field Radio Frequency Energy Harvesting for Passively Powered Sensor Networks. IEEE J. Solid State Circuits 43 (5) (2008)
James Ayers, Kartikeya Mayaram, Terri S. Fiez
A 0.4 nJ/b 900MHz CMOS BFSK super-regenerative receiver. CICC (2008)
Volodymyr Kratyuk, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram
A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy. IEEE Trans. Circuits Syst. II Express Briefs (3) (2007)
Ting Wu, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon
A 4.2 GHz PLL Frequency Synthesizer with an Adaptively Tuned Coarse Loop. CICC (2007)
Igor Vytyaz, David C. Lee, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram
Sensitivity analysis for oscillators. ICCAD (2007)
Christopher Hanken, Jim Le, Terri S. Fiez, Kartikeya Mayaram
Simulation and Modeling of Substrate Noise Generation from Synchronous and Asynchronous Digital Logic Circuits. CICC (2007)
James Ayers, Kartikeya Mayaram, Terri S. Fiez
Tradeoffs in the Design of CMOS Receivers for Low Power Wireless Sensor Networks. ISCAS (2007)
Volodymyr Kratyuk, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon
A 0.6GHz to 2GHz Digital PLL with Wide Tracking Range. CICC (2007)
Raghuram Jonnalagedda, Kartikeya Mayaram
Design of Very Low Noise 4.2GHz Clapp VCOs. ISCAS (2007)
Ting Wu, Kartikeya Mayaram, Un-Ku Moon
An On-chip Calibration Technique for Reducing Supply Voltage Sensitivity in Ring Oscillators. IEEE J. Solid State Circuits 42 (4) (2007)
Josh Carnes, Igor Vytyaz, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon
Design and Analysis of Noise Tolerant Ring Oscillators Using Maneatis Delay Cells. ICECS (2007)
Maneesha Yellepeddi, Kartikeya Mayaram
Issues in the Design and Simulation of a MEMS VCO based Phase-Locked Loop. ISCAS (2007)
Brett Peterson, Kartikeya Mayaram, Terri S. Fiez
Automated Extraction of Model Parameters for Noise Coupling Analysis in Silicon Substrates. CICC (2007)
James Ayers, Kartikeya Mayaram, Terri S. Fiez
A Low Power BFSK Super-Regenerative Transceiver. ISCAS (2007)
Pavan Kumar Hanumolu, Gu-Yeon Wei, Un-Ku Moon, Kartikeya Mayaram
Digitally-Enhanced Phase-Locking Circuits. CICC (2007)
Igor Vytyaz, David C. Lee, Suihua Lu, Amit Mehrotra, Un-Ku Moon, Kartikeya Mayaram
Periodic Steady-State Analysis of Oscillators with a Specified Oscillation Frequency. ISCAS (2007)
Igor Vytyaz, David C. Lee, Suihua Lu, Amit Mehrotra, Un-Ku Moon, Kartikeya Mayaram
Parameter Finding Methods for Oscillators with a Specified Oscillation Frequency. DAC (2007)
Janakiram G. Sankaranarayanan, Kartikeya Mayaram
Noise Simulation and Modeling for MEMS Varactor Based RF VCOs. ISCAS (2007)
Merrick Brownlee, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon
A 0.5-GHz to 2.5-GHz PLL With Fully Differential Supply Regulated Tuning. IEEE J. Solid State Circuits 41 (12) (2006)
Jim Le, Christopher Hanken, Martin Held, Michael S. Hagedorn, Kartikeya Mayaram, Terri S. Fiez
Comparison and Impact of Substrate Noise Generated by Clocked and Clockless Digital Circuitry. CICC (2006)
Ting Wu, Un-Ku Moon, Kartikeya Mayaram
Dependence of LC VCO oscillation frequency on bias current. ISCAS (2006)
Yutao Hu, Kartikeya Mayaram
Comparison of Algorithms for Frequency Domain Coupled Device and Circuit Simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (11) (2006)
Xiaochun Duan, Kartikeya Mayaram
Robust Simulation of High-Q Oscillators Using a Homotopy-Based Harmonic Balance Method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (12) (2006)
Kartikeya Mayaram
CEDA Currents. IEEE Des. Test Comput. 23 (2) (2006)
Merrick Brownlee, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon
A 0.5 to 2.5GHz PLL with Fully Differential Supply-Regulated Tuning. ISSCC (2006)
Triet Le, Jifeng Han, Annette R. von Jouanne, Kartikeya Mayaram, Terri S. Fiez
Piezoelectric micro-power generation interface circuits. IEEE J. Solid State Circuits 41 (6) (2006)
Arathi Sundaresan, Terri S. Fiez, Kartikeya Mayaram
Sizing Ground Taps to Minimize Substrate Noise Coupling in RF LNAs. CICC (2006)
Triet Le, Kartikeya Mayaram, Terri S. Fiez
Efficient Far-Field Radio Frequency Power Conversion System for Passively Powered Sensor Networks. CICC (2006)
Scott Hazenboom, Terri S. Fiez, Kartikeya Mayaram
A comparison of substrate noise coupling in lightly and heavily doped CMOS processes for 2.4-GHz LNAs. IEEE J. Solid State Circuits 41 (3) (2006)
Xiaochun Duan, Kartikeya Mayaram
Frequency-Domain Simulation of Ring Oscillators With a Multiple-Probe Method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (12) (2006)
Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram
An error control method for application of the discrete cosine transform to extraction of substrate parasitics in ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (5) (2006)
Patrick Birrer, Sasi Kumar Arunachalam, Martin Held, Kartikeya Mayaram, Terri S. Fiez
Schematic-Driven Substrate Noise Coupling Analysis in Mixed-Signal IC Designs. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2006)
Xiaochun Duan, Kartikeya Mayaram
A multiple-probe approach for robust frequency domain ring oscillator simulation. CICC (2005)
Chenggang Xu, Ranjit Gharpurey, Terri S. Fiez, Kartikeya Mayaram
A green function-based parasitic extraction method for inhomogeneous substrate layers. DAC (2005)
Ajit Sharma, Patrick Birrer, Sasi Kumar Arunachalam, Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram
Accurate Prediction of Substrate Parasitics in Heavily Doped CMOS Processes Using a Calibrated Boundary Element Solver. IEEE Trans. Very Large Scale Integr. Syst. 13 (7) (2005)
Xiaochun Duan, Kartikeya Mayaram
A new approach for ring oscillator simulation using the harmonic balance method. ASP-DAC (2005)
Xiaochun Duan, Kartikeya Mayaram
An efficient and robust method for ring-oscillator simulation using the harmonic-balance method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (8) (2005)
Ting Wu, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram
An FMDLL based dual-loop frequency synthesizer for 5 GHz WLAN applications. ISCAS (4) (2005)
Brian E. Owens, Sirisha Adluri, Patrick Birrer, Robert Shreeve, Sasi Kumar Arunachalam, Kartikeya Mayaram, Terri S. Fiez
Simulation and measurement of supply and substrate noise in mixed-signal ICs. IEEE J. Solid State Circuits 40 (2) (2005)
Husni M. Habal, Kartikeya Mayaram, Terri S. Fiez
Accurate and efficient simulation of synchronous digital switching noise in systems on a chip. IEEE Trans. Very Large Scale Integr. Syst. 13 (3) (2005)
Volodymyr Kratyuk, Igor Vytyaz, Un-Ku Moon, Kartikeya Mayaram
Analysis of supply and ground noise sensitivity in ring and LC oscillators. ISCAS (6) (2005)
Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram
On the numerical stability of Green's function for substrate coupling in integrated circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (4) (2005)
Volodymyr Kratyuk, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram
A low spur fractional-N frequency synthesizer architecture. ISCAS (3) (2005)
Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram
An improved Z-parameter macro model for substrate noise coupling. ISCAS (5) (2004)
Scott Hazenboom, Terri S. Fiez, Kartikeya Mayaram
Digital noise coupling mechanisms in a 2.4 GHz LNA for heavily and lightly doped CMOS substrates. CICC (2004)
Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram
An efficient formulation for substrate parasitic extraction accounting for nonuniform current distribution. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2004)
Zhao Li, Ravikanth Suravarapu, Roy Hartono, Sambuddha Bhattacharya, Kartikeya Mayaram, C.-J. Richard Shi
CrtSmile: a CAD tool for CMOS RF transistor substrate modeling incorporating layout effects. ASP-DAC (2004)
Manas Behera, Volodymyr Kratyuk, Yutao Hu, Kartikeya Mayaram
Accurate simulation of phase noise in RF MEMS VCOs. ISCAS (3) (2004)
Xiaochun Duan, Kartikeya Mayaram
Frequency domain simulation of high-Q oscillators with homotopy methods. ICCAD (2004)
Robert Shreeve, Terri S. Fiez, Kartikeya Mayaram
A physical and analytical model for substrate noise coupling analysis. ISCAS (5) (2004)
Ajit Sharma, Chenggang Xu, Wen Kung Chu, Nishath K. Verghese, Terri S. Fiez, Kartikeya Mayaram
A predictive methodology for accurate substrate parasitic extraction. ISCAS (5) (2004)
Patrick Birrer, Terri S. Fiez, Kartikeya Mayaram
Silencer!: a tool for substrate noise coupling analysis. SoCC (2004)
Yutao Hu, Kartikeya Mayaram
A modified-Volterra-series technique for improving the accuracy of quasi-static harmonic balance analysis in coupled device and circuit simulation. CICC (2004)
Husni M. Habal, Terri S. Fiez, Kartikeya Mayaram
An accurate and efficient estimation of switching noise in synchronous digital circuits. ISCAS (2) (2004)
Pavan Kumar Hanumolu, Merrick Brownlee, Kartikeya Mayaram, Un-Ku Moon
Analysis of charge-pump phase-locked loops. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2004)
Yutao Hu, Kartikeya Mayaram
A comparison of non-quasi-static and quasi-static harmonic balance implementations for coupled device and circuit simulation. CICC (2003)
Alicia Manthe, Zhao Li, C.-J. Richard Shi, Kartikeya Mayaram
Symbolic Analysis of Nonlinear Analog Circuits. DATE (2003)
Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram
Coupled Simulation of Circuit and Piezoelectric Laminates. ISQED (2003)
Triet Le, Jifeng Han, Annette R. von Jouanne, Kartikeya Mayaram, Terri S. Fiez
Piezoelectric power generation interface circuits. CICC (2003)
Brian E. Owens, Patrick Birrer, Sirisha Adluri, Robert Shreeve, Sasi Kumar Arunachalam, Husni Habal, Shu-Ching Hsu, Ajit Sharma, Kartikeya Mayaram, Terri S. Fiez
Strategies for simulation, measurement and suppression of digital noise in mixed-signal circuits. CICC (2003)
N. Seshan, J. Rajagopalan, Kartikeya Mayaram
Design of low power 2.4 GHz CMOS LC oscillators with low phase-noise and large tuning range. ISCAS (4) (2002)
V. Chandrasekhar, Kartikeya Mayaram
Analysis of CMOS RF LNAs with ESD protection. ISCAS (4) (2002)
Yutao Hu, Kartikeya Mayaram
An efficient algorithm for large-signal frequency-domain coupled device and circuit simulation [RF circuits]. ISCAS (5) (2002)
Nathen Barton, Dicle Özis, Terri S. Fiez, Kartikeya Mayaram
Analysis of jitter in ring oscillators due to deterministic noise. ISCAS (4) (2002)

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Publication Activity (10 Years)

Top Topics

Top Venues

Kartikeya Mayaram