C.-J. Richard Shi

ORCID

Publication Activity (10 Years)

Years Active: 1991-2024
Publications (10 Years): 52

Top Venues

ISCAS

IEEE J. Emerg. Sel. Topics Circuits Syst.

IEEE Trans. Circuits Syst. II Express Briefs

Integr.

Publications

Hao Zhu, Kefan Jin, Rui Gao, Jialin Wang, C.-J. Richard Shi
Timed-Elastic-Band Based Variable Splitting for Autonomous Trajectory Planning. CoRR (2024)
Tingxuan Liang, Ruizhi Liu, Lei Yang, Yue Lin, C.-J. Richard Shi, Hongtao Xu
Fall Detection System Based on Point Cloud Enhancement Model for 24 GHz FMCW Radar. Sensors 24 (2) (2024)
Jingsen Yang, Liangjian Lyu, Zirui Dong, Heyu Ren, C.-J. Richard Shi
A 28-nW Noise-Robust Voice Activity Detector with Background Aware Feature Extraction. A-SSCC (2023)
Yanhong Wang, Tianchan Guan, Dimin Niu, Qiaosha Zou, Hongzhong Zheng, C.-J. Richard Shi, Yuan Xie
Accelerating Distributed GNN Training by Codes. IEEE Trans. Parallel Distributed Syst. 34 (9) (2023)
Renze Gan, Liangjian Lyu, C.-J. Richard Shi
A 7-Channel Bio-Signal Analog Front End Employing Single-End Chopping Amplifier Achieving 1.48 NEF. ESSCIRC (2023)
Yanhong Wang, Zihao Zhao, Xu Jin, Haotian Zheng, Maohua Nie, Qiaosha Zou, C.-J. Richard Shi
AutoMap: Automatic Mapping of Neural Networks to Deep Learning Accelerators for Edge Devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (9) (2023)
Rongjin Xu, Dawei Ye, Sirou Li, C.-J. Richard Shi
65nm CMOS 2.5GHz Digital Injection-Locked Clock Multiplier with Injection Pulse Shaping Achieving -79dBc Reference Spur and 0.496mW/GHz Power Efficiency. ISSCC (2022)
Rongjin Xu, Dawei Ye, C.-J. Richard Shi
A 2.0-2.9 GHz ring-based injection-locked clock multiplier using a self-alignment frequency-tracking loop for reference spur reduction. Integr. 84 (2022)
Renze Gan, Liangjian Lyu, Geng Mu, C.-J. Richard Shi
A Neural Recording Analog Front-End with Exponentially Tunable Pseudo Resistors and On-Chip Digital Frequency Calibration Loop Achieving 3.4% Deviation of High-Pass Cutoff Frequency in 5-to-500 Hz Range. CICC (2022)
Zihao Zhao, Yanhong Wang, Qiaosha Zou, Tie Xu, Fangbo Tao, Jiansong Zhang, Xiaoan Wang, C.-J. Richard Shi, Junwen Luo, Yuan Xie
The Spike Gating Flow: A Hierarchical Structure Based Spiking Neural Network for Online Gesture Recognition. CoRR (2022)
Rongjin Xu, Dawei Ye, C.-J. Richard Shi
Analysis and Design of Digital Injection-Locked Clock Multipliers Using Bang-Bang Phase Detectors. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (7) (2022)
Dawei Ye, Rongjin Xu, C.-J. Richard Shi
Erratum to "A Nonlinear Receiver Leveraging Cascaded Inverter-Based Envelope-Biased LNAs for In-Band Interference Suppression in the Amplitude Domain". IEEE J. Solid State Circuits 57 (2) (2022)
Yanhong Wang, Qiaosha Zou, Yanmin Tang, Qing Wang, Jing Ding, Xin Wang, C.-J. Richard Shi
SAIL: A Deep-Learning-Based System for Automatic Gait Assessment From TUG Videos. IEEE Trans. Hum. Mach. Syst. 52 (1) (2022)
Junying Hu, C.-J. Richard Shi, Jiang-She Zhang
Saliency-based YOLO for single target detection. Knowl. Inf. Syst. 63 (3) (2021)
Shiwei Liu, Zihao Zhao, Yanhong Wang, Qiaosha Zou, Yiyun Zhang, C.-J. Richard Shi
Systolic-Array Deep-Learning Acceleration Exploring Pattern-Indexed Coordinate-Assisted Sparsity for Real-Time On-Device Speech Processing. ACM Great Lakes Symposium on VLSI (2021)
Chang Liu, Chun Zhao, C.-J. Richard Shi
A Fully-Synthesizable Fast-Response Digital LDO Using Automatic Offset Control and Reuse. ISCAS (2021)
Geng Mu, Dawei Ye, Liangjian Lyu, Xiaobin Zhao, C.-J. Richard Shi
An 8-Channel Analog Front-End with a PVT-lnsensitive Switched-Capacitor and Analog Combo DC Servo Loop Achieving 300mV Tolerance and 0.64s Recovery Time to Electrode-DC Offset for Physiological Signal Recording. CICC (2021)
Chang Liu, C.-J. Richard Shi
Design of the Class-E Power Amplifier Considering the Temperature Effect of the Transistor On-Resistance for Sensor Applications. IEEE Trans. Circuits Syst. II Express Briefs 68 (5) (2021)
Dawei Ye, Yuting Tu, Wenjun Gong, Rongjin Xu, C.-J. Richard Shi
A Two-Tone Wake-Up Receiver with an Envelope-Detector-First Architecture Using Envelope Biasing and Active Inductor Load Achieving 41/33dB In-Band Rejection to CW/AM Interference. A-SSCC (2021)
Dawei Ye, Rongjin Xu, C.-J. Richard Shi
A Nonlinear Receiver Leveraging Cascaded Inverter-Based Envelope-Biased LNAs for In-Band Interference Suppression in the Amplitude Domain. IEEE J. Solid State Circuits 56 (11) (2021)
Xingfa Qiu, Qiaosha Zou, C.-J. Richard Shi
Single-Pass On-Line Event Detection in Twitter Streams. ICMLC (2021)
Yuting Tu, Rongjin Xu, Dawei Ye, Liangjian Lyu, C.-J. Richard Shi
A 400 MHz, 8-Bit, 1.75-ps Resolution Pipelined-Two-Step Time-to-Digital Converter with Dynamic Time Amplification. ISCAS (2020)
Liangjian Lyu, Dawei Ye, C.-J. Richard Shi
A 340 nW/Channel 110 dB PSRR Neural Recording Analog Front-End Using Replica-Biasing LNA, Level-Shifter Assisted PGA, and Averaged LFP Servo Loop in 65 nm CMOS. IEEE Trans. Biomed. Circuits Syst. 14 (4) (2020)
Aili Wang, C.-J. Richard Shi
Analysis of Passive Charge Sharing-Based Segmented SAR ADCs. IEEE Trans. Very Large Scale Integr. Syst. 28 (5) (2020)
Liangjian Lyu, Yu Wang, Chixiao Chen, C.-J. Richard Shi
A 0.6V 1.07 μW/Channel neural interface IC using level-shifted feedback. Integr. 70 (2020)
Haozhe Zhu, Yu Wang, C.-J. Richard Shi
Tanji: a General-purpose Neural Network Accelerator with Unified Crossbar Architecture. IEEE Des. Test 37 (1) (2020)
Haozhe Zhu, Chixiao Chen, Shiwei Liu, Qiaosha Zou, Mingyu Wang, Lihua Zhang, Xiaoyang Zeng, C.-J. Richard Shi
A Communication-Aware DNN Accelerator on ImageNet Using In-Memory Entry-Counting Based Algorithm-Circuit-Architecture Co-Design in 65-nm CMOS. IEEE J. Emerg. Sel. Topics Circuits Syst. 10 (3) (2020)
Dawei Ye, Yu Wang, Yingfei Xiang, Liangjian Lyu, Hao Min, C.-J. Richard Shi
A Wireless Power and Data Transfer Receiver Achieving 75.4% Effective Power Conversion Efficiency and Supporting 0.1% Modulation Depth for ASK Demodulation. IEEE J. Solid State Circuits 55 (5) (2020)
Shiwei Liu, Haozhe Zhu, Chixiao Chen, Lihua Zhang, C.-J. Richard Shi
XNORAM: An Efficient Computing-in-Memory Architecture for Binary Convolutional Neural Networks with Flexible Dataflow Mapping. AICAS (2020)
Yitu Wang, Fan Chen, Linghao Song, C.-J. Richard Shi, Hai Helen Li, Yiran Chen
ReBoc: Accelerating Block-Circulant Neural Networks in ReRAM. DATE (2020)
Liangjian Lyu, Dawei Ye, Rongjin Xu, Geng Mu, Heng Zhao, Yingfei Xiang, Yuting Tu, Yiyun Zhang, C.-J. Richard Shi
A Fully-Integrated 64-Channel Wireless Neural Interfacing SoC Achieving 110 dB AFE PSRR and Supporting 54 Mb/s Symbol Rate, Meter-Range Wireless Data Transmission. IEEE Trans. Circuits Syst. II Express Briefs (5) (2020)
C.-J. Richard Shi, Aili Wang
Analysis of Bitwise and Samplewise Switched Passive Charge Sharing SAR ADCs. IEEE Trans. Very Large Scale Integr. Syst. 27 (9) (2019)
Chong Li, Kunyang Jia, Dan Shen, C.-J. Richard Shi, Hongxia Yang
Hierarchical Representation Learning for Bipartite Graphs. IJCAI (2019)
Liangjian Lyu, Yu Wang, Chixiao Chen, C.-J. Richard Shi
A low-voltage low-power multi-channel neural interface IC using level-shifted feedback technology. ASP-DAC (2019)
Dawei Ye, Rongjin Xu, C.-J. Richard Shi
A 2.4GHz 65nm CMOS Mixer-First Receiver Using 4-Stage Cascaded Inverter-Based Envelope-Biased LNAs Achieving 66dB In-Band Interference Tolerance and -83dBm Sensitivity. ISSCC (2019)
Dawei Ye, Rongjin Xu, Liangjian Lyu, C.-J. Richard Shi
A 2.46GHz, -88dBm Sensitivity CMOS Passive Mixer-First Nonlinear Receiver with >50dB Tolerance to In-Band Interferer. ISCAS (2019)
Liangjian Lyu, Dawei Ye, C.-J. Richard Shi
A 340nW/Channel Neural Recording Analog Front-End using Replica-Biasing LNAs to Tolerate 200mVpp Interfere from 350mV Power Supply. ISCAS (2019)
Aili Wang, Chixiao Chen, C.-J. Richard Shi
A 9-bit Resistor-Based All-Digital Temperature Sensor with a SAR-Quantization Embedded Differential Low-Pass Filter in 65nm CMOS Consuming 57pJ with a 2.5 μs Conversion Time. CICC (2019)
Chixiao Chen, Xindi Liu, Huwan Peng, Hongwei Ding, C.-J. Richard Shi
iFPNA: A Flexible and Efficient Deep Learning Processor in 28-nm CMOS Using a Domain-Specific Instruction Set and Reconfigurable Fabric. IEEE J. Emerg. Sel. Topics Circuits Syst. 9 (2) (2019)
Chixiao Chen, Huwan Peng, Xindi Liu, Hongwei Ding, C.-J. Richard Shi
Exploring the programmability for deep learning processors: from architecture to tensorization. DAC (2018)
Yu Wang, Dawei Ye, Liangjian Lyu, Yingfei Xiang, Hao Min, C.-J. Richard Shi
A 13.56MHz Wireless Power and Data Transfer Receiver Achieving 75.4% Effective-Power-Conversion Efficiency with 0.1% ASK Modulation Depth and 9.2mW Output Power. ISSCC (2018)
Ailing Piao, Aili Wang, C.-J. Richard Shi
Pin-Efficient 12-Bit 8-Wire 8-Level Permutation Coding for High-Speed Parallel Wireline Tranceivers. ISCAS (2018)
Aili Wang, C.-J. Richard Shi
A 10-bit 50-MS/s SAR ADC with 1 fJ/Conversion in 14 nm SOI FinFET CMOS. Integr. 62 (2018)
Yingfei Xiang, Yu Wang, C.-J. Richard Shi
A 13.56 MHz Active Rectifier With Self-Switching Comparator for Wireless Power Transfer Systems. ISOCC (2018)
Chong Li, C.-J. Richard Shi
Constrained Optimization Based Low-Rank Approximation of Deep Neural Networks. ECCV (10) (2018)
Chixiao Chen, Hongwei Ding, Huwan Peng, Haozhe Zhu, Yu Wang, C.-J. Richard Shi
OCEAN: An On-Chip Incremental-Learning Enhanced Artificial Neural Network Processor With Multiple Gated-Recurrent-Unit Accelerators. IEEE J. Emerg. Sel. Topics Circuits Syst. 8 (3) (2018)
Chixiao Chen, Xindi Liu, Huwan Peng, Hongwei Ding, C.-J. Richard Shi
iFPNA: A Flexible and Efficient Deep Neural Network Accelerator with a Programmable Data Flow Engine in 28nm CMOS. ESSCIRC (2018)
Yu Wang, Na Yan, Hao Min, C.-J. Richard Shi
A High-Efficiency Split-Merge Charge Pump for Solar Energy Harvesting. IEEE Trans. Circuits Syst. II Express Briefs (5) (2017)
Chixiao Chen, Hongwei Ding, Huwan Peng, Haozhe Zhu, Rui Ma, Peiyong Zhang, Xiaolang Yan, Yu Wang, Mingyu Wang, Hao Min, C.-J. Richard Shi
OCEAN: An on-chip incremental-learning enhanced processor with gated recurrent neural network accelerators. ESSCIRC (2017)
Allen Waters, Aili Wang, C.-J. Richard Shi
Highly time-interleaved noise-shaped SAR ADC with reconfigurable order. ISCAS (2016)
Aili Wang, Allen Waters, C.-J. Richard Shi
A sub-nW mV-range programmable threshold comparator for near-zero-energy sensing. ISCAS (2016)
Chong Li, Suriyaprakash Natarajan, C.-J. Richard Shi
Identifying DC bias conditions for maximum DC current in digitally-assisted analog design. ICECS (2015)
C.-J. Richard Shi
Mixed-signal system-on-chip verification using a recursively-verifying-modeling (RVM) methodology. ISCAS (2010)
Lihong Zhang, Yuping Zhang, Yingtao Jiang, C.-J. Richard Shi
Symmetry-aware placement algorithm using transitive closure graph representation for analog integrated circuits. Int. J. Circuit Theory Appl. 38 (3) (2010)
Bo Hu, C.-J. Richard Shi
Simulation of Closely Related Dynamic Nonlinear Systems With Application to Process-Voltage-Temperature Corner Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (5) (2008)
Yu-Te Liao, C.-J. Richard Shi
A 6-11GHz multi-phase VCO design with active inductors. ISCAS (2008)
Lihong Zhang, C.-J. Richard Shi, Yingtao Jiang
Symmetry-aware placement with transitive closure graphs for analog layout design. ASP-DAC (2008)
Lihong Zhang, Nuttorn Jangkrajarng, Sambuddha Bhattacharya, C.-J. Richard Shi
Parasitic-Aware Optimization and Retargeting of Analog Layouts: A Symbolic-Template Approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (5) (2008)
Lingzhi Liu, C.-J. Richard Shi
Sliced Message Passing: High Throughput Overlapped Decoding of High-Rate Low-Density Parity-Check Codes. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2008)
Yiyu Shi, Lei He, C.-J. Richard Shi
Scalable Symbolic Model Order Reduction. BMAS (2008)
Cherry Wakayama, Wolf Kohn, Zelda B. Zabinsky, C.-J. Richard Shi
A quantum-dot light-harvesting architecture using deterministic phase control. ISCAS (2008)
Pavel V. Nikitin, C.-J. Richard Shi
VHDL-AMS based modeling and simulation of mixed-technology microsystems: a tutorial. Integr. 40 (3) (2007)
Guoyong Shi, Weiwei Chen, C.-J. Richard Shi
A Graph Reduction Approach to Symbolic Circuit Analysis. ASP-DAC (2007)
Ming Su, Lili Zhou, C.-J. Richard Shi
Maximizing the throughput-area efficiency of fully-parallel low-density parity-check decoding with C-slow retiming and asynchronous deep pipelining. ICCD (2007)
Lili Zhou, Cherry Wakayama, C.-J. Richard Shi
CASCADE: A Standard Supercell Design Methodology With Congestion-Driven Placement for Three-Dimensional Interconnect-Heavy Very Large-Scale Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (7) (2007)
Lili Zhou, Cherry Wakayama, Robin Panda, Nuttorn Jangkrajarng, Bo Hu, C.-J. Richard Shi
Implementing a 2-Gbs 1024-bit 1/2-rate low-density parity-check code decoder in three-dimensional integrated circuits. ICCD (2007)
Lei Yang, Hui Liu, C.-J. Richard Shi
Code construction and FPGA implementation of a low-error-floor multi-rate low-density Parity-check code decoder. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2006)
Bo Hu, C.-J. Richard Shi
Improved automatic differentiation method for efficient model compiler. ISCAS (2006)
Zhao Li, C.-J. Richard Shi
A Quasi-Newton Preconditioned Newton-Krylov Method for Robust and Efficient Time-Domain Simulation of Integrated Circuits With Strong Parasitic Couplings. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (12) (2006)
Lili Zhou, Cherry Wakayama, Nuttorn Jangkrajarng, Bo Hu, C.-J. Richard Shi
A high-throughput low-power fully parallel 1024-bit 1/2-rate low density parity check code decoder in 3-dimensional integrated circuits. ASP-DAC (2006)
Zhao Li, C.-J. Richard Shi
SILCA: SPICE-accurate iterative linear-centric analysis for efficient time-domain Simulation of VLSI circuits with strong parasitic couplings. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (6) (2006)
Zhao Li, C.-J. Richard Shi
A quasi-newton preconditioned Newton-Krylov method for robust and efficient time-domain simulation of integrated circuits with strong parasitic couplings. ASP-DAC (2006)
Nuttorn Jangkrajarng, Lihong Zhang, Sambuddha Bhattacharya, Nathan Kohagen, C.-J. Richard Shi
Template-based parasitic-aware optimization and retargeting of analog and RF integrated circuit layouts. ICCAD (2006)
Sambuddha Bhattacharya, Nuttorn Jangkrajarng, C.-J. Richard Shi
Multilevel symmetry-constraint generation for retargeting large analog layouts. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (6) (2006)
C.-J. Richard Shi, Michael W. Tian, Guoyong Shi
Efficient DC fault simulation of nonlinear analog circuits: one-step relaxation and adaptive simulation continuation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (7) (2006)
Lei Yang, C.-J. Richard Shi
FROSTY: A program for fast extraction of high-level structural representation from circuit description for industrial CMOS circuits. Integr. 39 (4) (2006)
Guoyong Shi, Bo Hu, C.-J. Richard Shi
On symbolic model order reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (7) (2006)
Bo Hu, Zhao Li, Lili Zhou, C.-J. Richard Shi, Kwang-Hyun Baek, Myung-Jun Choe
Model-compiler based efficient statistical circuit analysis: an industry case study of a 4 GHz/6-bit ADC/DAC/DEMUX ASIC. ISCAS (6) (2005)
Lei Yang, Hui Liu, C.-J. Richard Shi
VLSI implementation of a low-error-floor and capacity-approaching low-density parity-check code decoder with multi-rate capacity. GLOBECOM (2005)
Bo Hu, C.-J. Richard Shi
Fast-yet-accurate PVT simulation by combined direct and iterative methods. ICCAD (2005)
Vikram Jandhyala, Yasuo Kuga, David J. Allstot, C.-J. Richard Shi
Bridging Circuits and Electromagnetics in a Curriculum Aimed at Microelectronic Analog and Microwave Simulation and Design. MSE (2005)
Lei Yang, Manyuan Shen, Hui Liu, C.-J. Richard Shi
An FPGA implementation of low-density parity-check code decoder with multi-rate capability. ASP-DAC (2005)
Roy Hartono, Nuttorn Jangkrajarng, Sambuddha Bhattacharya, C.-J. Richard Shi
Automatic Device Layout Generation for Analog Layout Retargeting. VLSI Design (2005)
Guoyong Shi, C.-J. Richard Shi
Model-order reduction by dominant subspace projection: error bound, subspace computation, and circuit applications. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2005)
Lei Yang, Cherry Wakayama, C.-J. Richard Shi
Noise aware behavioral modeling of the E-Delta fractional-N frequency synthesizer. ACM Great Lakes Symposium on VLSI (2005)
Sambuddha Bhattacharya, Nuttorn Jangkrajarng, C.-J. Richard Shi
Template-driven parasitic-aware optimization of analog integrated circuit layouts. DAC (2005)
Zhao Li, C.-J. Richard Shi
An Efficiently Preconditioned GMRES Method for Fast Parasitic-Sensitive Deep-Submicron VLSI Circuit Simulation. DATE (2005)
Guoyong Shi, C.-J. Richard Shi
Parametric reduced order modeling for interconnect analysis. ASP-DAC (2004)
Zhao Li, Ravikanth Suravarapu, Roy Hartono, Sambuddha Bhattacharya, Kartikeya Mayaram, C.-J. Richard Shi
CrtSmile: a CAD tool for CMOS RF transistor substrate modeling incorporating layout effects. ASP-DAC (2004)
Zhao Li, C.-J. Richard Shi
A coupled iterative/direct method for efficient time-domain simulation of nonlinear circuits with power/ground networks. ISCAS (5) (2004)
Pavel V. Nikitin, Vikram Jandhyala, Daniel A. White, Nathan Champagne, John D. Rockway, C.-J. Richard Shi, Chuanyi Yang, Yong Wang, Gong Ouyang, Rob Sharpe, John W. Rockway
Modeling and Simulation of Circuit-Electromagnetic Effects in Electronic Design Flow. ISQED (2004)
Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Roy Hartono, C.-J. Richard Shi
Hierarchical extraction and verification of symmetry constraints for analog layout automation. ASP-DAC (2004)
Bo Wan, C.-J. Richard Shi
Hierarchical Multi-Dimensional Table Lookup for Model Compiler Based Circuit Simulation. DATE (2004)
Sheldon X.-D. Tan, C.-J. Richard Shi
Efficient approximation of symbolic expressions for analog behavioral modeling and analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (6) (2004)
Nuttorn Jangkrajarng, Sambuddha Bhattacharya, Roy Hartono, C.-J. Richard Shi
Multiple specifications radio-frequency integrated circuit design with automatic template-driven layout retargeting. ASP-DAC (2004)
Bo Wan, Pavel V. Nikitin, C.-J. Richard Shi
Circuit level modeling and simulation of mixed-technology systems. SoCC (2004)
Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Roy Hartono, C.-J. Richard Shi
Correct-by-construction layout-centric retargeting of large analog designs. DAC (2004)
Sheldon X.-D. Tan, C.-J. Richard Shi, Jyh-Chwen Lee
Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (12) (2003)
Alicia Manthe, Zhao Li, C.-J. Richard Shi
Symbolic analysis of analog circuits with hard nonlinearity. DAC (2003)
Bo Wan, Bo P. Hu, Lili Zhou, C.-J. Richard Shi
MCAST: an abstract-syntax-tree based model compiler for circuit simulation. CICC (2003)

C.-J. Richard Shi.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

C.-J. Richard Shi