Dimin Niu

Publication Activity (10 Years)

Years Active: 2010-2024
Publications (10 Years): 34

Top Topics

Service Architecture

Matrix Multiplication

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Teng Ma, Zheng Liu, Chengkun Wei, Jialiang Huang, Youwei Zhuo, Haoyu Li, Ning Zhang, Yijin Guan, Dimin Niu, Mingxing Zhang, Tao Ma
HydraRPC: RPC in the CXL Era. USENIX ATC (2024)
Zhiyao Li, Jiaxiang Li, Taijie Chen, Dimin Niu, Hongzhong Zheng, Yuan Xie, Mingyu Gao
Spada: Accelerating Sparse Matrix Multiplication with Adaptive Dataflow. ASPLOS (2) (2023)
Xinfeng Xie, Peng Gu, Yufei Ding, Dimin Niu, Hongzhong Zheng, Yuan Xie
MPU: Memory-centric SIMT Processor via In-DRAM Near-bank Computing. ACM Trans. Archit. Code Optim. 20 (3) (2023)
Zheng Qu, Dimin Niu, Shuangchen Li, Hongzhong Zheng, Yuan Xie
TT-GNN: Efficient On-Chip Graph Neural Network Training via Embedding Reformation and Hardware Optimization. MICRO (2023)
Xuanle Ren, Zhaohui Chen, Zhen Gu, Yanheng Lu, Ruiguang Zhong, Wen-Jie Lu, Jiansong Zhang, Yichi Zhang, Hanghang Wu, Xiaofu Zheng, Heng Liu, Tingqiang Chu, Cheng Hong, Changzheng Wei, Dimin Niu, Yuan Xie
CHAM: A Customized Homomorphic Encryption Accelerator for Fast Matrix-Vector Product. DAC (2023)
Zhenhua Zhu, Hanbo Sun, Tongxin Xie, Yu Zhu, Guohao Dai, Lixue Xia, Dimin Niu, Xiaoming Chen, Xiaobo Sharon Hu, Yu Cao, Yuan Xie, Huazhong Yang, Yu Wang
MNSIM 2.0: A Behavior-Level Modeling Tool for Processing-In-Memory Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (11) (2023)
Yanhong Wang, Tianchan Guan, Dimin Niu, Qiaosha Zou, Hongzhong Zheng, C.-J. Richard Shi, Yuan Xie
Accelerating Distributed GNN Training by Codes. IEEE Trans. Parallel Distributed Syst. 34 (9) (2023)
Cong Li, Zhe Zhou, Xingchen Li, Guangyu Sun, Dimin Niu
NMExplorer: An Efficient Exploration Framework for DIMM-based Near-Memory Tensor Reduction. DAC (2023)
Linyong Huang, Zhe Zhang, Shuangchen Li, Dimin Niu, Yijin Guan, Hongzhong Zheng, Yuan Xie
Practical Near-Data-Processing Architecture for Large-Scale Distributed Graph Neural Network. IEEE Access 10 (2022)
Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Hongzhong Zheng, Yuan Xie
Accelerating CPU-Based Sparse General Matrix Multiplication With Binary Row Merging. IEEE Access 10 (2022)
Xingchen Li, Zhihang Yuan, Yijin Guan, Guangyu Sun, Tao Zhang, Rongshan Wei, Dimin Niu
Flatfish: A Reinforcement Learning Approach for Application-Aware Address Mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (11) (2022)
Haozhe Zhu, Bo Jiao, Jinshan Zhang, Xinru Jia, Yunzhengmao Wang, Tianchan Guan, Shengcheng Wang, Dimin Niu, Hongzhong Zheng, Chixiao Chen, Mingyu Wang, Lihua Zhang, Xiaoyang Zeng, Qi Liu, Yuan Xie, Ming Liu
COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning. ISSCC (2022)
Shuangchen Li, Dimin Niu, Yuhao Wang, Wei Han, Zhe Zhang, Tianchan Guan, Yijin Guan, Heng Liu, Linyong Huang, Zhaoyang Du, Fei Xue, Yuanwei Fang, Hongzhong Zheng, Yuan Xie
Hyperscale FPGA-as-a-service architecture for large-scale distributed graph neural network. ISCA (2022)
Xingchen Li, Bingzhe Wu, Guangyu Sun, Zhe Zhang, Zhihang Yuan, Runsheng Wang, Ru Huang, Dimin Niu, Hongzhong Zheng, Zhichao Lu, Liang Zhao, Meng-Fan Marvin Chang, Tianchan Guan, Xin Si
Enabling High-Quality Uncertainty Quantification in a PIM Designed for Bayesian Neural Network. HPCA (2022)
Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Linyong Huang, Hongzhong Zheng, Yuan Xie
OpSparse: a Highly Optimized Framework for Sparse General Matrix Multiplication on GPUs. CoRR (2022)
Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Hongzhong Zheng, Yuan Xie
Accelerating CPU-based Sparse General Matrix Multiplication with Binary Row Merging. CoRR (2022)
Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Linyong Huang, Hongzhong Zheng, Yuan Xie
OpSparse: A Highly Optimized Framework for Sparse General Matrix Multiplication on GPUs. IEEE Access 10 (2022)
Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Nianxiong Tan, Xiaopeng Yu, Hongzhong Zheng, Jianyi Meng, Xiaolang Yan, Yuan Xie
Predicting the Output Structure of Sparse Matrix Multiplication with Sampled Compression Ratio. CoRR (2022)
Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Nianxiong Tan, Xiaopeng Yu, Hongzhong Zheng, Jianyi Meng, Xiaolang Yan, Yuan Xie
Predicting the Output Structure of Sparse Matrix Multiplication with Sampled Compression Ratio. ICPADS (2022)
Dimin Niu, Shuangchen Li, Yuhao Wang, Wei Han, Zhe Zhang, Yijin Guan, Tianchan Guan, Fei Sun, Fei Xue, Lide Duan, Yuanwei Fang, Hongzhong Zheng, Xiping Jiang, Song Wang, Fengguo Zuo, Yubing Wang, Bing Yu, Qiwei Ren, Yuan Xie
3D Logic-to-DRAM Hybrid Bonding with Process-Near-Memory Engine for Recommendation System. ISSCC (2022)
Xinfeng Xie, Peng Gu, Yufei Ding, Dimin Niu, Hongzhong Zheng, Yuan Xie
MPU: Towards Bandwidth-abundant SIMT Processor via Near-bank Computing. CoRR (2021)
Feng Wang, Guojie Luo, Guang-Yu Sun, Yuhao Wang, Dimin Niu, Hongzhong Zheng
Area Efficient Pattern Representation of Binary Neural Networks on RRAM. J. Comput. Sci. Technol. 36 (5) (2021)
Feng Wang, Guojie Luo, Guangyu Sun, Jiaxi Zhang, Jinfeng Kang, Yuhao Wang, Dimin Niu, Hongzhong Zheng
STAR: Synthesis of Stateful Logic in RRAM Targeting High Area Utilization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (5) (2021)
Peng Gu, Xinfeng Xie, Shuangchen Li, Dimin Niu, Hongzhong Zheng, Krishna T. Malladi, Yuan Xie
DLUX: A LUT-Based Near-Bank Accelerator for Data Center Deep Learning Training Workloads. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (8) (2021)
Zhao Wang, Yijin Guan, Guangyu Sun, Dimin Niu, Yuhao Wang, Hongzhong Zheng, Yinhe Han
GNN-PIM: A Processing-in-Memory Architecture for Graph Neural Networks. ACA (2020)
Peng Gu, Xinfeng Xie, Yufei Ding, Guoyang Chen, Weifeng Zhang, Dimin Niu, Yuan Xie
iPIM: Programmable In-Memory Image Processing Accelerator Using Near-Bank Architecture. ISCA (2020)
Zhenhua Zhu, Hanbo Sun, Kaizhong Qiu, Lixue Xia, Gokul Krishnan, Guohao Dai, Dimin Niu, Xiaoming Chen, Xiaobo Sharon Hu, Yu Cao, Yuan Xie, Yu Wang, Huazhong Yang
MNSIM 2.0: A Behavior-Level Modeling Tool for Memristor-based Neuromorphic Computing Systems. ACM Great Lakes Symposium on VLSI (2020)
Youwei Zhuo, Chao Wang, Mingxing Zhang, Rui Wang, Dimin Niu, Yanzhi Wang, Xuehai Qian
GraphQ: Scalable PIM-Based Graph Processing. MICRO (2019)
Shuangchen Li, Alvin Oliver Glova, Xing Hu, Peng Gu, Dimin Niu, Krishna T. Malladi, Hongzhong Zheng, Bob Brennan, Yuan Xie
SCOPE: A Stochastic Computing Engine for DRAM-Based In-Situ Accelerator. MICRO (2018)
Mu-Tien Chang, I. Stephen Choi, Dimin Niu, Hongzhong Zheng
Performance Impact of Emerging Memory Technologies on Big Data Applications: A Latency-Programmable System Emulation Approach. ACM Great Lakes Symposium on VLSI (2018)
Shuangchen Li, Dimin Niu, Krishna T. Malladi, Hongzhong Zheng, Bob Brennan, Yuan Xie
DRISA: a DRAM-based reconfigurable in-situ accelerator. MICRO (2017)
Mingyu Gao, Christina Delimitrou, Dimin Niu, Krishna T. Malladi, Hongzhong Zheng, Bob Brennan, Christos Kozyrakis
DRAF: A Low-Power DRAM-Based Reconfigurable Acceleration Fabric. IEEE Micro 37 (3) (2017)
Krishna T. Malladi, Mu-Tien Chang, Dimin Niu, Hongzhong Zheng
FlashStorageSim: Performance Modeling for SSD Architectures. NAS (2017)
Mingyu Gao, Christina Delimitrou, Dimin Niu, Krishna T. Malladi, Hongzhong Zheng, Bob Brennan, Christos Kozyrakis
DRAF: A Low-Power DRAM-Based Reconfigurable Acceleration Fabric. ISCA (2016)
Cong Xu, Dimin Niu, Naveen Muralimanohar, Rajeev Balasubramonian, Tao Zhang, Shimeng Yu, Yuan Xie
Overcoming the challenges of crossbar resistive memory architectures. HPCA (2015)
Cong Xu, Yang Zheng, Dimin Niu, Xiaochun Zhu, Seung H. Kang, Yuan Xie
Impact of Write Pulse and Process Variation on 22 nm FinFET-Based STT-RAM Design: A Device-Architecture Co-Optimization Approach. IEEE Trans. Multi Scale Comput. Syst. 1 (4) (2015)
Cong Xu, Dimin Niu, Yang Zheng, Shimeng Yu, Yuan Xie
Impact of Cell Failure on Reliable Cross-Point Resistive Memory Design. ACM Trans. Design Autom. Electr. Syst. 20 (4) (2015)
Cong Xu, Dimin Niu, Shimeng Yu, Yuan Xie
Modeling and design analysis of 3D vertical resistive memory - A low cost cross-point architecture. ASP-DAC (2014)
Qiaosha Zou, Dimin Niu, Yan Cao, Yuan Xie
3DLAT: TSV-based 3D ICs crosstalk minimization utilizing Less Adjacent Transition code. ASP-DAC (2014)
Cong Xu, Pai-Yu Chen, Dimin Niu, Yang Zheng, Shimeng Yu, Yuan Xie
Architecting 3D vertical resistive memory for next-generation storage systems. ICCAD (2014)
Chao Zhang, Guangyu Sun, Peng Li, Tao Wang, Dimin Niu, Yiran Chen
SBAC: a statistics based cache bypassing method for asymmetric-access caches. ISLPED (2014)
Cong Xu, Dimin Niu, Yang Zheng, Shimeng Yu, Yuan Xie
Reliability-aware cross-point resistive memory design. ACM Great Lakes Symposium on VLSI (2014)
Cong Xu, Dimin Niu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie
Understanding the trade-offs in multi-level cell ReRAM memory design. DAC (2013)
Dimin Niu, Qiaosha Zou, Cong Xu, Yuan Xie
Low power multi-level-cell resistive memory design with incomplete data mapping. ICCD (2013)
Dimin Niu, Cong Xu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie
Design of cross-point metal-oxide ReRAM emphasizing reliability and cost. ICCAD (2013)
Dimin Niu, Cong Xu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie
Design trade-offs for high density cross-point resistive memory. ISLPED (2012)
Dimin Niu, Yang Xiao, Yuan Xie
Low power memristor-based ReRAM design with Error Correcting Code. ASP-DAC (2012)
Jin Ouyang, Chuan Yang, Dimin Niu, Yuan Xie, Zhiwen Liu
BFLY: an on-chip free-space optical network with wavelength-switching. ICS (2011)
Guangyu Sun, Dimin Niu, Jin Ouyang, Yuan Xie
A frequent-value based PRAM memory architecture. ASP-DAC (2011)
Cong Xu, Dimin Niu, Xiaochun Zhu, Seung H. Kang, Matt Nowak, Yuan Xie
Device-architecture co-optimization of STT-RAM based memory for low power embedded systems. ICCAD (2011)
Jue Wang, Xiangyu Dong, Guangyu Sun, Dimin Niu, Yuan Xie
Energy-efficient multi-level cell phase-change memory system with data encoding. ICCD (2011)
Yibo Chen, Dimin Niu, Yuan Xie, Krishnendu Chakrabarty
Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis. ICCAD (2010)
Dimin Niu, Yibo Chen, Xiangyu Dong, Yuan Xie
Energy and performance driven circuit design for emerging phase-change memory. ASP-DAC (2010)
Dimin Niu, Yiran Chen, Yuan Xie
Low-power dual-element memristor based memory design. ISLPED (2010)
Yongsoo Joo, Dimin Niu, Xiangyu Dong, Guangyu Sun, Naehyuck Chang, Yuan Xie
Energy- and endurance-aware design of phase change memory caches. DATE (2010)
Dimin Niu, Yiran Chen, Cong Xu, Yuan Xie
Impact of process variations on emerging memristor. DAC (2010)
Guangyu Sun, Yongsoo Joo, Yibo Chen, Dimin Niu, Yuan Xie, Yiran Chen, Hai Li
A Hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement. HPCA (2010)