Naveen Muralimanohar

Publication Activity (10 Years)

Years Active: 2005-2018
Publications (10 Years): 6

Top Topics

Convolutional Neural Network

Enabling Technologies

Top Venues

Publications

Anirban Nag, Rajeev Balasubramonian, Vivek Srikumar, Ross Walker, Ali Shafiee, John Paul Strachan, Naveen Muralimanohar
Newton: Gravitating Towards the Physical Limits of Crossbar Acceleration. IEEE Micro 38 (5) (2018)
Anirban Nag, Ali Shafiee, Rajeev Balasubramonian, Vivek Srikumar, Naveen Muralimanohar
Newton: Gravitating Towards the Physical Limits of Crossbar Acceleration. CoRR (2018)
Rajeev Balasubramonian, Andrew B. Kahng, Naveen Muralimanohar, Ali Shafiee, Vaishnav Srinivas
CACTI 7: New Tools for Interconnect Exploration in Innovative Off-Chip Memories. ACM Trans. Archit. Code Optim. 14 (2) (2017)
Ali Shafiee, Anirban Nag, Naveen Muralimanohar, Rajeev Balasubramonian, John Paul Strachan, Miao Hu, R. Stanley Williams, Vivek Srikumar
ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars. ISCA (2016)
Arjun Deb, Paolo Faraboschi, Ali Shafiee, Naveen Muralimanohar, Rajeev Balasubramonian, Robert Schreiber
Enabling technologies for memory compression: Metadata, mapping, and prediction. ICCD (2016)
Babak Falsafi, Mircea Stan, Kevin Skadron, Nuwan Jayasena, Yunji Chen, Jinhua Tao, Ravi Nair, Jaime H. Moreno, Naveen Muralimanohar, Karthikeyan Sankaralingam, Cristian Estan
Near-Memory Data Services. IEEE Micro 36 (1) (2016)
Norman P. Jouppi, Andrew B. Kahng, Naveen Muralimanohar, Vaishnav Srinivas
CACTI-IO: CACTI With OFF-Chip Power-Area-Timing Models. IEEE Trans. Very Large Scale Integr. Syst. 23 (7) (2015)
Cong Xu, Dimin Niu, Naveen Muralimanohar, Rajeev Balasubramonian, Tao Zhang, Shimeng Yu, Yuan Xie
Overcoming the challenges of crossbar resistive memory architectures. HPCA (2015)
Manjunath Shevgoor, Naveen Muralimanohar, Rajeev Balasubramonian, Yoocharn Jeon
Improving memristor memory with sneak current sharing. ICCD (2015)
Ke Chen, Sheng Li, Jung Ho Ahn, Naveen Muralimanohar, Jishen Zhao, Cong Xu, Seongil O, Yuan Xie, Jay B. Brockman, Norman P. Jouppi
History-Assisted Adaptive-Granularity Caches (HAAG$) for High Performance 3D DRAM Architectures. ICS (2015)
HanBin Yoon, Justin Meza, Naveen Muralimanohar, Norman P. Jouppi, Onur Mutlu
Efficient Data Mapping and Buffering Techniques for Multilevel Cell Phase-Change Memories. ACM Trans. Archit. Code Optim. 11 (4) (2014)
Cong Xu, Dimin Niu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie
Understanding the trade-offs in multi-level cell ReRAM memory design. DAC (2013)
Dimin Niu, Cong Xu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie
Design of cross-point metal-oxide ReRAM emphasizing reliability and cost. ICCAD (2013)
Nathan L. Binkert, Al Davis, Norman P. Jouppi, Moray McLaren, Naveen Muralimanohar, Robert Schreiber, Jung Ho Ahn
Optical High Radix Switch Design. IEEE Micro 32 (3) (2012)
Niladrish Chatterjee, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi
Staged Reads: Mitigating the impact of DRAM writes on DRAM reads. HPCA (2012)
Ke Chen, Sheng Li, Naveen Muralimanohar, Jung Ho Ahn, Jay B. Brockman, Norman P. Jouppi
CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory. DATE (2012)
Doe Hyun Yoon, Naveen Muralimanohar, Jichuan Chang, Parthasarathy Ranganathan, Norman P. Jouppi, Mattan Erez
Free-p: A Practical End-to-End Nonvolatile Memory Protection Mechanism. IEEE Micro 32 (3) (2012)
Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi
LOT-ECC: Localized and tiered reliability mechanisms for commodity memory systems. ISCA (2012)
Doe Hyun Yoon, Jichuan Chang, Naveen Muralimanohar, Parthasarathy Ranganathan
BOOM: Enabling mobile memory based low-power server DIMMs. ISCA (2012)
Dimin Niu, Cong Xu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie
Design trade-offs for high density cross-point resistive memory. ISLPED (2012)
Norman P. Jouppi, Andrew B. Kahng, Naveen Muralimanohar, Vaishnav Srinivas
CACTI-IO: CACTI with off-chip power-area-timing models. ICCAD (2012)
Nathan L. Binkert, Al Davis, Norman P. Jouppi, Moray McLaren, Naveen Muralimanohar, Robert Schreiber, Jung Ho Ahn
The role of optics in future high radix switch design. ISCA (2011)
Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi
Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems. ISCA (2011)
Xiangyu Dong, Yuan Xie, Naveen Muralimanohar, Norman P. Jouppi
Hybrid checkpointing using emerging nonvolatile memories for future exascale systems. ACM Trans. Archit. Code Optim. 8 (2) (2011)
Doe Hyun Yoon, Naveen Muralimanohar, Jichuan Chang, Parthasarathy Ranganathan, Norman P. Jouppi, Mattan Erez
FREE-p: Protecting non-volatile memory against both hard and soft errors. HPCA (2011)
Sheng Li, Ke Chen, Ming-yu Hsieh, Naveen Muralimanohar, Chad D. Kersey, Jay B. Brockman, Arun F. Rodrigues, Norman P. Jouppi
System implications of memory reliability in exascale computing. SC (2011)
Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian
Towards scalable, energy-efficient, bus-based on-chip networks. HPCA (2010)
Aniruddha N. Udipi, Naveen Muralimanohar, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi
Rethinking DRAM design and organization for energy-constrained multi-cores. ISCA (2010)
Xiangyu Dong, Yuan Xie, Naveen Muralimanohar, Norman P. Jouppi
Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support. SC (2010)
Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian
Non-uniform power access in large caches with low-swing wires. HiPC (2009)
Xiangyu Dong, Naveen Muralimanohar, Norman P. Jouppi, Richard Kaufmann, Yuan Xie
Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems. SC (2009)
Niti Madan, Li Zhao, Naveen Muralimanohar, Aniruddha N. Udipi, Rajeev Balasubramonian, Ravishankar R. Iyer, Srihari Makineni, Donald Newell
Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy. HPCA (2009)
Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi
Architecting Efficient Interconnects for Large Caches with CACTI 6.0. IEEE Micro 28 (1) (2008)
Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen Muralimanohar, Rajeev Balasubramonian
Scalable and reliable communication for hardware transactional memory. PACT (2008)
Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0. MICRO (2007)
Naveen Muralimanohar, Rajeev Balasubramonian
Interconnect design considerations for large NUCA caches. ISCA (2007)
Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian
Power efficient resource scaling in partitioned architectures through dynamic heterogeneity. ISPASS (2006)
Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Liqun Cheng, John B. Carter
Leveraging Wire Properties at the Microarchitecture Level. IEEE Micro 26 (6) (2006)
Liqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, John B. Carter
Interconnect-Aware Coherence Protocols for Chip Multiprocessors. ISCA (2006)
Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Venkatanand Venkatachalapathy
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures. HPCA (2005)