Rajeev Balasubramonian

Publication Activity (10 Years)

Years Active: 2000-2024
Publications (10 Years): 35

Top Topics

Top Venues

Publications

Lin Jia, James Patrick Mcmahon, Sumanth Gudaparthi, Shreyas Singh, Rajeev Balasubramonian
PATHFINDER: Practical Real-Time Learning for Data Prefetching. ASPLOS (3) (2024)
Sarabjeet Singh, Xiong Fan, Ananth Krishna Prasad, Lin Jia, Anirban Nag, Rajeev Balasubramonian, Mahdi Nazm Bojnordi, Elaine Shi
XCRYPT: Accelerating Lattice Based Cryptography with Memristor Crossbar Arrays. CoRR (2023)
Sarabjeet Singh, Xiong Fan, Ananth Krishna Prasad, Lin Jia, Anirban Nag, Rajeev Balasubramonian, Mahdi Nazm Bojnordi, Elaine Shi
XCRYPT: Accelerating Lattice-Based Cryptography With Memristor Crossbar Arrays. IEEE Micro 43 (5) (2023)
Zhao Chang, Dong Xie, Feifei Li, Jeff M. Phillips, Rajeev Balasubramonian
Efficient and Oblivious Query Processing for Range and kNN Queries (Extended Abstract). ICDE (2022)
Zhao Chang, Dong Xie, Feifei Li, Jeff M. Phillips, Rajeev Balasubramonian
Efficient Oblivious Query Processing for Range and kNN Queries. IEEE Trans. Knowl. Data Eng. 34 (12) (2022)
Amlan Ganguly, Sergi Abadal, Ishan G. Thakkar, Natalie Enright Jerger, Marc D. Riedel, Masoud Babaie, Rajeev Balasubramonian, Abu Sebastian, Sudeep Pasricha, Baris Taskin
Interconnects for DNA, Quantum, In-Memory, and Optical Computing: Insights From a Panel Discussion. IEEE Micro 42 (3) (2022)
Sumanth Gudaparthi, Sarabjeet Singh, Surya Narayanan, Rajeev Balasubramonian, Visvesh Sathe
CANDLES: Channel-Aware Novel Dataflow-Microarchitecture Co-Design for Low Energy Sparse Neural Network Acceleration. HPCA (2022)
Anirban Nag, Rajeev Balasubramonian
OrderLight: Lightweight Memory-Ordering Primitive for Efficient Fine-Grained PIM Computations. MICRO (2021)
Adarsh Patil, Vijay Nagarajan, Rajeev Balasubramonian, Nicolai Oswald
Dvé: Improving DRAM Reliability and Performance On-Demand via Coherent Replication. ISCA (2021)
Surya Narayanan, Karl Taht, Rajeev Balasubramonian, Edouard Giacomin, Pierre-Emmanuel Gaillardon
SpinalFlow: An Architecture and Dataflow Tailored for Spiking Neural Networks. ISCA (2020)
Meysam Taassori, Rajeev Balasubramonian, Siddhartha Chhabra, Alaa R. Alameldeen, Manjula Peddireddy, Rajat Agarwal, Ryan Stutsman
Compact Leakage-Free Support for Integrity and Reliability. ISCA (2020)
Sumanth Gudaparthi, Surya Narayanan, Rajeev Balasubramonian, Edouard Giacomin, Hari Kambalasubramanyam, Pierre-Emmanuel Gaillardon
Wire-Aware Architecture and Dataflow for CNN Accelerators. MICRO (2019)
Anirban Nag, C. N. Ramachandra, Rajeev Balasubramonian, Ryan Stutsman, Edouard Giacomin, Hari Kambalasubramanyam, Pierre-Emmanuel Gaillardon
GenCache: Leveraging In-Cache Operators for Efficient Sequence Alignment. MICRO (2019)
Chandrasekhar Nagarajan, Ali Shafiee, Rajeev Balasubramonian, Mohit Tiwari
ρ: Relaxed Hierarchical ORAM. ASPLOS (2019)
Karl Taht, James Greensky, Rajeev Balasubramonian
The POP Detector: A Lightweight Online Program Phase Detection Framework. ISPASS (2019)
Andrew Vuong, Ali Shafiee, Meysam Taassori, Rajeev Balasubramonian
An MLP-aware leakage-free memory controller. HASP@ISCA (2018)
Anirban Nag, Rajeev Balasubramonian, Vivek Srikumar, Ross Walker, Ali Shafiee, John Paul Strachan, Naveen Muralimanohar
Newton: Gravitating Towards the Physical Limits of Crossbar Acceleration. IEEE Micro 38 (5) (2018)
Ali Shafiee, Rajeev Balasubramonian, Mohit Tiwari, Feifei Li
Secure DIMM: Moving ORAM Primitives Closer to Memory. HPCA (2018)
Anirban Nag, Ali Shafiee, Rajeev Balasubramonian, Vivek Srikumar, Naveen Muralimanohar
Newton: Gravitating Towards the Physical Limits of Crossbar Acceleration. CoRR (2018)
Meysam Taassori, Ali Shafiee, Rajeev Balasubramonian
VAULT: Reducing Paging Overheads in SGX with Efficient Integrity Verification Structures. ASPLOS (2018)
Sumanth Gudaparthi, Surya Narayanan, Rajeev Balasubramonian
Moving CNN Accelerator Computations Closer to Data. EMC2@ASPLOS (2018)
Karl Taht, Surya Narayanan, Rajeev Balasubramonian
A Case for Dynamic Activation Quantization in CNNs. EMC2@ASPLOS (2018)
Rajeev Balasubramonian, Andrew B. Kahng, Naveen Muralimanohar, Ali Shafiee, Vaishnav Srinivas
CACTI 7: New Tools for Interconnect Exploration in Innovative Off-Chip Memories. ACM Trans. Archit. Code Optim. 14 (2) (2017)
Karl Taht, Rajeev Balasubramonian
Introspective Computing. PACT (2017)
Surya Narayanan, Ali Shafiee, Rajeev Balasubramonian
INXS: Bridging the throughput and energy gap for spiking neural networks. IJCNN (2017)
Ali Shafiee, Anirban Nag, Naveen Muralimanohar, Rajeev Balasubramonian, John Paul Strachan, Miao Hu, R. Stanley Williams, Vivek Srikumar
ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars. ISCA (2016)
Arjun Deb, Paolo Faraboschi, Ali Shafiee, Naveen Muralimanohar, Rajeev Balasubramonian, Robert Schreiber
Enabling technologies for memory compression: Metadata, mapping, and prediction. ICCD (2016)
Rajeev Balasubramonian, Boris Grot
Near-Data Processing [Guest editors' introduction]. IEEE Micro 36 (1) (2016)
Manjunath Shevgoor, Rajeev Balasubramonian, Niladrish Chatterjee, Jung-Sik Kim
Addressing service interruptions in memory with thread-to-rank assignment. ISPASS (2016)
Meysam Taassori, Ali Shafiee, Rajeev Balasubramonian
Understanding and alleviating intra-die and intra-DIMM parameter variation in the memory system. ICCD (2016)
Seth H. Pugsley, Arjun Deb, Rajeev Balasubramonian, Feifei Li
Fixed-function hardware sorting accelerators for near data MapReduce execution. ICCD (2015)
Cong Xu, Dimin Niu, Naveen Muralimanohar, Rajeev Balasubramonian, Tao Zhang, Shimeng Yu, Yuan Xie
Overcoming the challenges of crossbar resistive memory architectures. HPCA (2015)
Manjunath Shevgoor, Naveen Muralimanohar, Rajeev Balasubramonian, Yoocharn Jeon
Improving memristor memory with sneak current sharing. ICCD (2015)
Manjunath Shevgoor, Sahil Koladiya, Rajeev Balasubramonian, Chris Wilkerson, Seth H. Pugsley, Zeshan Chishti
Efficiently prefetching complex address patterns. MICRO (2015)
Ali Shafiee, Akhila Gundu, Manjunath Shevgoor, Rajeev Balasubramonian, Mohit Tiwari
Avoiding information leakage in the memory controller with fixed service policies. MICRO (2015)
Niladrish Chatterjee, Mike O'Connor, Gabriel H. Loh, Nuwan Jayasena, Rajeev Balasubramonian
Managing DRAM Latency Divergence in Irregular GPGPU Applications. SC (2014)
Ali Shafiee, Meysam Taassori, Rajeev Balasubramonian, Al Davis
MemZip: Exploring unconventional benefits from memory compression. HPCA (2014)
Akhila Gundu, Gita Sreekumar, Ali Shafiee, Seth H. Pugsley, Hardik B. Jain, Rajeev Balasubramonian, Mohit Tiwari
Memory bandwidth reservation in the cloud to avoid information leakage in the memory controller. HASP@ISCA (2014)
Rajeev Balasubramonian, Jichuan Chang, Troy Manning, Jaime H. Moreno, Richard Murphy, Ravi Nair, Steven Swanson
Near-Data Processing: Insights from a MICRO-46 Workshop. IEEE Micro 34 (4) (2014)
Seth H. Pugsley, Jeffrey Jestes, Rajeev Balasubramonian, Vijayalakshmi Srinivasan, Alper Buyuktosunoglu, Al Davis, Feifei Li
Comparing Implementations of Near-Data Computing with In-Memory MapReduce Workloads. IEEE Micro 34 (4) (2014)
Seth H. Pugsley, Jeffrey Jestes, Huihui Zhang, Rajeev Balasubramonian, Vijayalakshmi Srinivasan, Alper Buyuktosunoglu, Al Davis, Feifei Li
NDC: Analyzing the impact of 3D-stacked memory+logic devices on MapReduce workloads. ISPASS (2014)
Seth H. Pugsley, Zeshan Chishti, Chris Wilkerson, Peng-fei Chuang, Robert L. Scott, Aamer Jaleel, Shih-Lien Lu, Kingsum Chow, Rajeev Balasubramonian
Sandbox Prefetching: Safe run-time evaluation of aggressive prefetchers. HPCA (2014)
Kshitij Sudan, Saisanthosh Balakrishnan, Sean Lie, Min Xu, Dhiraj Mallick, Gary Lauterbach, Rajeev Balasubramonian
A novel system architecture for web scale applications using lightweight CPUs and virtualized I/O. HPCA (2013)
Manjunath Shevgoor, Jung-Sik Kim, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, Aniruddha N. Udipi
Quantifying the relationship between the power delivery network and architectural policies in a 3D-stacked memory device. MICRO (2013)
Niladrish Chatterjee, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi
Staged Reads: Mitigating the impact of DRAM writes on DRAM reads. HPCA (2012)
Niladrish Chatterjee, Manjunath Shevgoor, Rajeev Balasubramonian, Al Davis, Zhen Fang, Ramesh Illikkal, Ravi R. Iyer
Leveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word Access. MICRO (2012)
Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi
LOT-ECC: Localized and tiered reliability mechanisms for commodity memory systems. ISCA (2012)
Manu Awasthi, David W. Nellans, Kshitij Sudan, Rajeev Balasubramonian, Al Davis
Managing Data Placement in Memory Systems with Multiple Memory Controllers. Int. J. Parallel Program. 40 (1) (2012)
Kshitij Sudan, Sadagopan Srinivasan, Rajeev Balasubramonian, Ravi R. Iyer
Optimizing datacenter power with memory system levers for guaranteed quality-of-service. PACT (2012)
Manu Awasthi, Manjunath Shevgoor, Kshitij Sudan, Bipin Rajendran, Rajeev Balasubramonian, Viji Srinivasan
Efficient scrub mechanisms for error-prone emerging memories. HPCA (2012)
Manu Awasthi, David W. Nellans, Rajeev Balasubramonian, Al Davis
Prediction Based DRAM Row-Buffer Management in the Many-Core Era. PACT (2011)
Xiaowei Jiang, Niti Madan, Li Zhao, Mike Upton, Ravishankar R. Iyer, Srihari Makineni, Donald Newell, Yan Solihin, Rajeev Balasubramonian
CHOP: Integrating DRAM Caches for CMP Server Platforms. IEEE Micro 31 (1) (2011)
Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi
Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems. ISCA (2011)
Gagandeep S. Sachdev, Kshitij Sudan, Mary W. Hall, Rajeev Balasubramonian
Understanding the Behavior of Pthread Applications on Non-Uniform Cache Architectures. PACT (2011)
Kshitij Sudan, Niladrish Chatterjee, David W. Nellans, Manu Awasthi, Rajeev Balasubramonian, Al Davis
Micro-pages: increasing DRAM efficiency with locality-aware data placement. ASPLOS (2010)
David W. Nellans, Kshitij Sudan, Rajeev Balasubramonian, Erik Brunvand
Hardware prediction of OS run-length for fine-grained resource customization. ISPASS (2010)
Seth H. Pugsley, Josef B. Spjut, David W. Nellans, Rajeev Balasubramonian
SWEL: hardware cache coherence protocols to map shared data onto shared caches. PACT (2010)
Manu Awasthi, David W. Nellans, Kshitij Sudan, Rajeev Balasubramonian, Al Davis
Handling the problems and opportunities posed by multiple on-chip memory controllers. PACT (2010)
Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian
Towards scalable, energy-efficient, bus-based on-chip networks. HPCA (2010)
David W. Nellans, Kshitij Sudan, Erik Brunvand, Rajeev Balasubramonian
Improving Server Performance on Multi-cores via Selective Off-Loading of OS Functionality. ISCA Workshops (2010)
Aniruddha N. Udipi, Naveen Muralimanohar, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi
Rethinking DRAM design and organization for energy-constrained multi-cores. ISCA (2010)
Xiaowei Jiang, Niti Madan, Li Zhao, Mike Upton, Ravishankar R. Iyer, Srihari Makineni, Donald Newell, Yan Solihin, Rajeev Balasubramonian
CHOP: Adaptive filter-based DRAM caching for CMP server platforms. HPCA (2010)
Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian
Non-uniform power access in large caches with low-swing wires. HiPC (2009)
Manu Awasthi, Kshitij Sudan, Rajeev Balasubramonian, John B. Carter
Dynamic hardware-assisted software-controlled page placement to manage capacity allocation and sharing within large caches. HPCA (2009)
Niti Madan, Li Zhao, Naveen Muralimanohar, Aniruddha N. Udipi, Rajeev Balasubramonian, Ravishankar R. Iyer, Srihari Makineni, Donald Newell
Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy. HPCA (2009)
David W. Nellans, Rajeev Balasubramonian, Erik Brunvand
OS execution on multi-cores: is out-sourcing worthwhile? ACM SIGOPS Oper. Syst. Rev. 43 (2) (2009)
Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi
Architecting Efficient Interconnects for Large Caches with CACTI 6.0. IEEE Micro 28 (1) (2008)
Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen Muralimanohar, Rajeev Balasubramonian
Scalable and reliable communication for hardware transactional memory. PACT (2008)
Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0. MICRO (2007)
Manu Awasthi, Vivek Venkatesan, Rajeev Balasubramonian
Understanding the Impact of 3D Stacked Layouts on ILP. J. Instr. Level Parallelism 9 (2007)
Niti Madan, Rajeev Balasubramonian
Leveraging 3D Technology for Improved Reliability. MICRO (2007)
Niti Madan, Rajeev Balasubramonian
Power Efficient Approaches to Redundant Multithreading. IEEE Trans. Parallel Distributed Syst. 18 (8) (2007)
Naveen Muralimanohar, Rajeev Balasubramonian
Interconnect design considerations for large NUCA caches. ISCA (2007)
Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian
Power efficient resource scaling in partitioned architectures through dynamic heterogeneity. ISPASS (2006)
Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Liqun Cheng, John B. Carter
Leveraging Wire Properties at the Microarchitecture Level. IEEE Micro 26 (6) (2006)
Liqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, John B. Carter
Interconnect-Aware Coherence Protocols for Chip Multiprocessors. ISCA (2006)
Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Venkatanand Venkatachalapathy
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures. HPCA (2005)
Rajeev Balasubramonian
Cluster prefetch: tolerating on-chip wire delays in clustered microarchitectures. ICS (2004)
David H. Albonesi, Rajeev Balasubramonian, Steve Dropsho, Sandhya Dwarkadas, Eby G. Friedman, Michael C. Huang, Volkan Kursun, Grigorios Magklis, Michael L. Scott, Greg Semeraro, Pradip Bose, Alper Buyuktosunoglu, Peter W. Cook, Stanley Schuster
Dynamically Tuning Processor Resources with Adaptive Processing. Computer 36 (12) (2003)
Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas
A Dynamically Tunable Memory Hierarchy. IEEE Trans. Computers 52 (10) (2003)
Rajeev Balasubramonian, Viji Srinivasan, Sandhya Dwarkadas, Alper Buyuktosunoglu
Hot-and-Cold: Using Criticality in the Design of Energy-Efficient Caches. PACS (2003)
Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi
Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered Processors. ISCA (2003)
Greg Semeraro, Grigorios Magklis, Rajeev Balasubramonian, David H. Albonesi, Sandhya Dwarkadas, Michael L. Scott
Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling. HPCA (2002)
Steve Dropsho, Alper Buyuktosunoglu, Rajeev Balasubramonian, David H. Albonesi, Sandhya Dwarkadas, Greg Semeraro, Grigorios Magklis, Michael L. Scott
Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power. IEEE PACT (2002)
Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi
Dynamically allocating processor resources between nearby and distant ILP. ISCA (2001)
Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi
Reducing the complexity of the register file in dynamic superscalar processors. MICRO (2001)
Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures. MICRO (2000)