Aamer Jaleel

Publication Activity (10 Years)

Years Active: 2001-2024
Publications (10 Years): 41

Top Topics

Top Venues

Publications

Moinuddin Qureshi, Salman Qazi, Aamer Jaleel
MINT: Securely Mitigating Rowhammer with a Minimalist In-DRAM Tracker. CoRR (2024)
Yueqi Wang, Bingyao Li, Aamer Jaleel, Jun Yang, Xulong Tang
GRIT: Enhancing Multi-GPU Performance with Fine-Grained Dynamic Page Placement. HPCA (2024)
Moinuddin K. Qureshi, Anish Saxena, Aamer Jaleel
ImPress: Securing DRAM Against Data-Disturbance Errors via Implicit Row-Press Mitigation. CoRR (2024)
Aamer Jaleel, Gururaj Saileshwar, Stephen W. Keckler, Moinuddin K. Qureshi
PrIDE: Achieving Secure Rowhammer Mitigation with Low-Cost In-DRAM Trackers. ISCA (2024)
Aamer Jaleel, Stephen W. Keckler, Gururaj Saileshwar
Probabilistic Tracker Management Policies for Low-Cost and Scalable Rowhammer Mitigation. CoRR (2024)
Bingyao Li, Yueqi Wang, Tianyu Wang, Lieven Eeckhout, Jun Yang, Aamer Jaleel, Xulong Tang
Improving Multi-Instance GPU Efficiency via Sub-Entry Sharing TLB Design. CoRR (2024)
Mohamed Tarek Ibn Ziad, Sana Damani, Aamer Jaleel, Stephen W. Keckler, Mark Stephenson
cuCatch: A Debugging Tool for Efficiently Catching Memory Safety Violations in CUDA Applications. Proc. ACM Program. Lang. 7 (PLDI) (2023)
Michael Pellauer, Jason Clemons, Vignesh Balaji, Neal Clayton Crago, Aamer Jaleel, Donghyuk Lee, Mike O'Connor, Anghsuman Parashar, Sean Treichler, Po-An Tsai, Stephen W. Keckler, Joel S. Emer
Symphony: Orchestrating Sparse and Dense Tensors with Hierarchical Heterogeneous Processing. ACM Trans. Comput. Syst. 41 (2023)
Toluwanimi O. Odemuyiwa, Hadi Asghari Moghaddam, Michael Pellauer, Kartik Hegde, Po-An Tsai, Neal Clayton Crago, Aamer Jaleel, John D. Owens, Edgar Solomonik, Joel S. Emer, Christopher W. Fletcher
Accelerating Sparse Data Orchestration via Dynamic Reflexive Tiling. ASPLOS (3) (2023)
Toluwanimi O. Odemuyiwa, Hadi Asghari Moghaddam, Michael Pellauer, Kartik Hegde, Po-An Tsai, Neal Clayton Crago, Aamer Jaleel, John D. Owens, Edgar Solomonik, Joel S. Emer, Christopher W. Fletcher
Accelerating Sparse Data Orchestration via Dynamic Reflexive Tiling (Extended Abstract). HOPC@SPAA (2023)
Michael B. Sullivan, Mohamed Tarek Ibn Ziad, Aamer Jaleel, Stephen W. Keckler
Implicit Memory Tagging: No-Overhead Memory Safety Using Alias-Free Tagged ECC. ISCA (2023)
Vignesh Balaji, Neal Clayton Crago, Aamer Jaleel, Stephen W. Keckler
Community-based Matrix Reordering for Sparse Linear Algebra Optimization. ISPASS (2023)
Yaosheng Fu, Evgeny Bolotin, Aamer Jaleel, Gal Dalal, Shie Mannor, Jacob Subag, Noam Korem, Michael Behar, David W. Nellans
AutoScratch: ML-Optimized Cache Management for Inference-Oriented GPUs. MLSys (2023)
Bingyao Li, Yanan Guo, Yueqi Wang, Aamer Jaleel, Jun Yang, Xulong Tang
IDYLL: Enhancing Page Translation in Multi-GPUs via Light Weight PTE Invalidations. MICRO (2023)
Vignesh Balaji, Neal Clayton Crago, Aamer Jaleel, Brandon Lucia
P-OPT: Practical Optimal Cache Replacement for Graph Analytics. HPCA (2021)
Xiaowei Ren, Daniel Lustig, Evgeny Bolotin, Aamer Jaleel, Oreste Villa, David W. Nellans
HMG: Extending Cache Coherence Protocols Across Modern Hierarchical Multi-GPU Systems. HPCA (2020)
Aamer Jaleel, Eiman Ebrahimi, Sam Duncan
DUCATI: High-performance Address Translation by Extending TLB Reach of GPU-accelerated Systems. ACM Trans. Archit. Code Optim. 16 (1) (2019)
Kartik Hegde, Hadi Asghari Moghaddam, Michael Pellauer, Neal Clayton Crago, Aamer Jaleel, Edgar Solomonik, Joel S. Emer, Christopher W. Fletcher
ExTensor: An Accelerator for Sparse Tensor Algebra. MICRO (2019)
Xia Zhao, Almutaz Adileh, Zhibin Yu, Zhiying Wang, Aamer Jaleel, Lieven Eeckhout
Adaptive memory-side last-level GPU caching. ISCA (2019)
Vinson Young, Chia-Chen Chou, Aamer Jaleel, Moinuddin K. Qureshi
ACCORD: Enabling Associativity for Gigascale DRAM Caches by Coordinating Way-Install and Way-Prediction. ISCA (2018)
Vinson Young, Aamer Jaleel, Evgeny Bolotin, Eiman Ebrahimi, David W. Nellans, Oreste Villa
Combining HW/SW Mechanisms to Improve NUMA Performance of Multi-GPU Systems. MICRO (2018)
Mwaffaq Otoom, Aamer Jaleel, Pedro Trancoso
Using Personality Metrics to Improve Cache Interference Management in Multicore Processors. Conf. Computing Frontiers (2017)
Aamer Jaleel, Moinuddin K. Qureshi
Top Picks from the 2016 Computer Architecture Conferences. IEEE Micro 37 (3) (2017)
Mehmet Kayaalp, Khaled N. Khasawneh, Hodjat Asghari Esfeden, Jesse Elwell, Nael B. Abu-Ghazaleh, Dmitry V. Ponomarev, Aamer Jaleel
RIC: Relaxed Inclusion Caches for Mitigating LLC Side-Channel Attacks. DAC (2017)
Chia-Chen Chou, Aamer Jaleel, Moinuddin K. Qureshi
BATMAN: techniques for maximizing system bandwidth of memory systems with stacked-DRAM. MEMSYS (2017)
Akhil Arunkumar, Evgeny Bolotin, Benjamin Y. Cho, Ugljesa Milic, Eiman Ebrahimi, Oreste Villa, Aamer Jaleel, Carole-Jean Wu, David W. Nellans
MCM-GPU: Multi-Chip-Module GPUs for Continued Performance Scalability. ISCA (2017)
Almutaz Adileh, Stijn Eyerman, Aamer Jaleel, Lieven Eeckhout
Mind The Power Holes: Sifting Operating Points in Power-Limited Heterogeneous Multicores. IEEE Comput. Archit. Lett. 16 (1) (2017)
Ugljesa Milic, Oreste Villa, Evgeny Bolotin, Akhil Arunkumar, Eiman Ebrahimi, Aamer Jaleel, Alex Ramírez, David W. Nellans
Beyond the socket: NUMA-aware GPUs. MICRO (2017)
Hsiang-Yun Cheng, Jishen Zhao, Jack Sampson, Mary Jane Irwin, Aamer Jaleel, Yu Lu, Yuan Xie
LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches. ISCA (2016)
Mehmet Kayaalp, Nael B. Abu-Ghazaleh, Dmitry V. Ponomarev, Aamer Jaleel
A high-resolution side-channel attack on last-level cache. DAC (2016)
Joshua San Miguel, Jorge Albericio, Natalie D. Enright Jerger, Aamer Jaleel
The Bunker Cache for spatio-value approximation. MICRO (2016)
Mohsen Ghasempour, Aamer Jaleel, Jim D. Garside, Mikel Luján
HAPPY: Hybrid Address-based Page Policy in DRAMs. MEMSYS (2016)
Chia-Chen Chou, Aamer Jaleel, Moinuddin K. Qureshi
CANDY: Enabling coherent DRAM caches for multi-node systems. MICRO (2016)
Mohsen Ghasempour, Aamer Jaleel, Jim D. Garside, Mikel Luján
DReAM: Dynamic Re-arrangement of Address Mapping to Improve the Performance of DRAMs. MEMSYS (2016)
Almutaz Adileh, Stijn Eyerman, Aamer Jaleel, Lieven Eeckhout
Maximizing Heterogeneous Processor Performance Under Power Constraints. ACM Trans. Archit. Code Optim. 13 (3) (2016)
Chia-Chen Chou, Aamer Jaleel, Moinuddin K. Qureshi
BEAR: techniques for mitigating bandwidth bloat in gigascale DRAM caches. ISCA (2015)
Mohsen Ghasempour, Aamer Jaleel, Jim D. Garside, Mikel Luján
HAPPY: Hybrid Address-based Page Policy in DRAMs. CoRR (2015)
Mohsen Ghasempour, Jim D. Garside, Aamer Jaleel, Mikel Luján
DReAM: Dynamic Re-arrangement of Address Mapping to Improve the Performance of DRAMs. CoRR (2015)
Muhammet Mustafa Ozdal, Aamer Jaleel, Paolo Narváez, Steven M. Burns, Ganapati Srinivasa
Wavelet-Based Trace Alignment Algorithms for Heterogeneous Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (3) (2015)
Aamer Jaleel, Joseph Nuzman, Adrian Moga, Simon C. Steely Jr., Joel S. Emer
High performing cache hierarchies for server workloads: Relaxing inclusion to capture the latency benefits of exclusive caches. HPCA (2015)
Michael Pellauer, Angshuman Parashar, Michael Adler, Bushra Ahsan, Randy L. Allmon, Neal Clayton Crago, Kermin Fleming, Mohit Gambhir, Aamer Jaleel, Tushar Krishna, Daniel Lustig, Stephen Maresh, Vladimir Pavlov, Rachid Rayess, Antonia Zhai, Joel S. Emer
Efficient Control and Communication Paradigms for Coarse-Grained Spatial Architectures. ACM Trans. Comput. Syst. 33 (3) (2015)
Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Clayton Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy L. Allmon, Rachid Rayess, Stephen Maresh, Joel S. Emer
Efficient Spatial Processing Element Control via Triggered Instructions. IEEE Micro 34 (3) (2014)
Chia-Chen Chou, Aamer Jaleel, Moinuddin K. Qureshi
CAMEO: A Two-Level Memory Organization with Capacity of Main Memory and Flexibility of Hardware-Managed Cache. MICRO (2014)
Wim Heirman, Trevor E. Carlson, Kenzo Van Craeynest, Ibrahim Hur, Aamer Jaleel, Lieven Eeckhout
Undersubscribed threading on clustered cache architectures. HPCA (2014)
Wim Heirman, Trevor E. Carlson, Kenzo Van Craeynest, Ibrahim Hur, Aamer Jaleel, Lieven Eeckhout
Automatic SMT threading for OpenMP applications on the Intel Xeon Phi co-processor. ROSS@ICS (2014)
Seth H. Pugsley, Zeshan Chishti, Chris Wilkerson, Peng-fei Chuang, Robert L. Scott, Aamer Jaleel, Shih-Lien Lu, Kingsum Chow, Rajeev Balasubramonian
Sandbox Prefetching: Safe run-time evaluation of aggressive prefetchers. HPCA (2014)
Kenzo Van Craeynest, Shoaib Akram, Wim Heirman, Aamer Jaleel, Lieven Eeckhout
Fairness-aware scheduling on single-ISA heterogeneous multi-cores. PACT (2013)
Muhammet Mustafa Ozdal, Aamer Jaleel, Paolo Narváez, Steven M. Burns, Ganapati Srinivasa
Trace alignment algorithms for offline workload analysis of heterogeneous architectures. ICCAD (2013)
Samantika Subramaniam, Simon C. Steely Jr., William Hasenplaugh, Aamer Jaleel, Carl J. Beckmann, Tryggve Fossum, Joel S. Emer
Using in-flight chains to build a scalable cache coherence protocol. ACM Trans. Archit. Code Optim. 10 (4) (2013)
Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Clayton Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy L. Allmon, Rachid Rayess, Stephen Maresh, Joel S. Emer
Triggered instructions: a control paradigm for spatially-programmed architectures. ISCA (2013)
Kenzo Van Craeynest, Aamer Jaleel, Lieven Eeckhout, Paolo Narváez, Joel S. Emer
Scheduling heterogeneous multi-cores through performance impact estimation (PIE). ISCA (2012)
Aamer Jaleel, Hashem Hashemi Najaf-abadi, Samantika Subramaniam, Simon C. Steely Jr., Joel S. Emer
CRUISE: cache replacement and utility-aware scheduling. ASPLOS (2012)
Leonid Domnitser, Aamer Jaleel, Jason Loew, Nael B. Abu-Ghazaleh, Dmitry Ponomarev
Non-monopolizable caches: Low-complexity mitigation of cache side channel attacks. ACM Trans. Archit. Code Optim. 8 (4) (2012)
William Hasenplaugh, Pritpal S. Ahuja, Aamer Jaleel, Simon C. Steely Jr., Joel S. Emer
The gradient-based cache partitioning algorithm. ACM Trans. Archit. Code Optim. 8 (4) (2012)
Binh Pham, Viswanathan Vaidyanathan, Aamer Jaleel, Abhishek Bhattacharjee
CoLT: Coalesced Large-Reach TLBs. MICRO (2012)
Carole-Jean Wu, Aamer Jaleel, Margaret Martonosi, Simon C. Steely Jr., Joel S. Emer
PACMan: prefetch-aware cache management for high performance caching. MICRO (2011)
Carole-Jean Wu, Aamer Jaleel, William Hasenplaugh, Margaret Martonosi, Simon C. Steely Jr., Joel S. Emer
SHiP: signature-based hit predictor for high performance caching. MICRO (2011)
Aamer Jaleel, Kevin B. Theobald, Simon C. Steely Jr., Joel S. Emer
High performance cache replacement using re-reference interval prediction (RRIP). ISCA (2010)
Aamer Jaleel, Eric Borch, Malini Bhandaru, Simon C. Steely Jr., Joel S. Emer
Achieving Non-Inclusive Cache Performance with Inclusive Caches: Temporal Locality Aware (TLA) Cache Management Policies. MICRO (2010)
Arijit Biswas, Charles Recchia, Shubhendu S. Mukherjee, Vinod Ambrose, Leo Chan, Aamer Jaleel, Athanasios E. Papathanasiou, Mike Plaster, Norbert Seifert
Explaining cache SER anomaly using DUE AVF measurement. HPCA (2010)
Moshe Bach, Mark Charney, Robert Cohn, Elena Demikhovsky, Tevi Devor, Kim M. Hazelwood, Aamer Jaleel, Chi-Keung Luk, Gail Lyons, Harish Patil, Ady Tal
Analyzing Parallel Programs with Pin. Computer 43 (3) (2010)
Jaideep Moses, Konstantinos Aisopos, Aamer Jaleel, Ravi R. Iyer, Ramesh Illikkal, Donald Newell, Srihari Makineni
CMPSched$im: Evaluating OS/CMP interaction on shared cache management. ISPASS (2009)
Junmin Lin, Yu Chen, Wenlong Li, Aamer Jaleel, Zhizhong Tang
Understanding the Memory Behavior of Emerging Multi-core Workloads. ISPDC (2009)
Yu Chen, Wenlong Li, Junmin Lin, Aamer Jaleel, Zhizhong Tang
Data Sharing Analysis of Emerging Parallel Media Mining Workloads. HiPC (2008)
Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely Jr., Joel S. Emer
Set-Dueling-Controlled Adaptive Insertion for High-Performance Caching. IEEE Micro 28 (1) (2008)
Aamer Jaleel, William Hasenplaugh, Moinuddin K. Qureshi, Julien Sebot, Simon C. Steely Jr., Joel S. Emer
Adaptive insertion policies for managing shared caches. PACT (2008)
Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely Jr., Joel S. Emer
Adaptive insertion policies for high performance caching. ISCA (2007)
Erez Perelman, Jeremy Lau, Harish Patil, Aamer Jaleel, Greg Hamerly, Brad Calder
Cross Binary Simulation Points. ISPASS (2007)
Brinda Ganesh, Aamer Jaleel, David Wang, Bruce L. Jacob
Fully-Buffered DIMM Memory Architectures: Understanding Mechanisms, Overheads and Scaling. HPCA (2007)
Wenlong Li, Eric Q. Li, Aamer Jaleel, Jiulong Shan, Yurong Chen, Qigang Wang, Ravi R. Iyer, Ramesh Illikkal, Yimin Zhang, Dong Liu, Michael Liao, Wei Wei, Jinhua Du
Understanding the Memory Performance of Data-Mining Workloads on Small, Medium, and Large-Scale CMPs Using Hardware-Software Co-simulation. ISPASS (2007)
Aamer Jaleel, Matthew Mattina, Bruce L. Jacob
Last level cache (LLC) performance of data mining workloads on a CMP - a case study of parallel bioinformatics workloads. HPCA (2006)
Aamer Jaleel, Bruce L. Jacob
In-Line Interrupt Handling and Lock-Up Free Translation Lookaside Buffers (TLBs). IEEE Trans. Computers 55 (5) (2006)
Kursad Albayraktaroglu, Aamer Jaleel, Xue Wu, Manoj Franklin, Bruce L. Jacob, Chau-Wen Tseng, Donald Yeung
BioBench: A Benchmark Suite of Bioinformatics Applications. ISPASS (2005)
David Wang, Brinda Ganesh, Nuengwong Tuaycharoen, Kathleen Baynes, Aamer Jaleel, Bruce L. Jacob
DRAMsim: a memory system simulator. SIGARCH Comput. Archit. News 33 (4) (2005)
Aamer Jaleel, Bruce L. Jacob
Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions. HPCA (2005)
Aamer Jaleel, Bruce L. Jacob
In-Line Interrupt Handling for Software-Managed TLBs. ICCD (2001)
Aamer Jaleel, Bruce L. Jacob
Improving the Precise Interrupt Mechanism of Software-Managed TLB Miss Handlers. HiPC (2001)