Stijn Eyerman

Publication Activity (10 Years)

Years Active: 2006-2024
Publications (10 Years): 30

Top Topics

Top Venues

IEEE Comput. Archit. Lett.

ACM Trans. Archit. Code Optim.

Publications

Stijn Eyerman, Wim Heirman, Kristof Du Bois, Ibrahim Hur
Accurate and Scalable Many-Node Simulation. CoRR (2024)
Wim Heirman, Stijn Eyerman
Message from the Program Chairs; ISPASS 2024. ISPASS (2024)
Sriram Aananthakrishnan, Shamsul Abedin, Vincent Cavé, Fabio Checconi, Kristof Du Bois, Stijn Eyerman, Joshua B. Fryman, Wim Heirman, Jason Howard, Ibrahim Hur, Samkit Jain, Marek M. Landowski, Kevin Ma, Jarrod A. Nelson, Robert Pawlowski, Fabrizio Petrini, Sebastian Szkoda, Sanjaya Tayal, Jesmin Jahan Tithi, Yves Vandriessche
The Intel Programmable and Integrated Unified Memory Architecture Graph Analytics Processor. IEEE Micro 43 (5) (2023)
Stijn Eyerman, Sam Van den Steen, Wim Heirman, Ibrahim Hur
Simulating Wrong-Path Instructions in Decoupled Functional-First Simulation. ISPASS (2023)
Stijn Eyerman, Wim Heirman, Ibrahim Hur
DRAM Bandwidth and Latency Stacks: Visualizing DRAM Bottlenecks. ISPASS (2022)
Wenjie Liu, Wim Heirman, Stijn Eyerman, Shoaib Akram, Lieven Eeckhout
Scale-Model Architectural Simulation. ISPASS (2022)
Stijn Eyerman, Ibrahim Hur
Efficient Asynchronous RPC Calls for Microservices: DeathStarBench Study. CoRR (2022)
Dimitri Kagaris, Sourav Dutta, Stijn Eyerman
Execution Time Estimation of Multithreaded Programs With Critical Sections. IEEE Trans. Parallel Distributed Syst. 33 (10) (2022)
Stijn Eyerman, Wim Heirman, Sam Van den Steen, Ibrahim Hur
Enabling Branch-Mispredict Level Parallelism by Selectively Flushing Instructions. MICRO (2021)
Wenjie Liu, Wim Heirman, Stijn Eyerman, Shoaib Akram, Lieven Eeckhout
Scale-Model Simulation. IEEE Comput. Archit. Lett. 20 (2) (2021)
Stijn Eyerman, Wim Heirman, Ibrahim Hur
Modeling DRAM Timing in Parallel Simulators With Immediate-Response Memory Model. IEEE Comput. Archit. Lett. 20 (2) (2021)
Wim Heirman, Stijn Eyerman, Kristof Du Bois, Ibrahim Hur
Automatic Sublining for Efficient Sparse Memory Accesses. ACM Trans. Archit. Code Optim. 18 (3) (2021)
Wim Heirman, Stijn Eyerman, Kristof Du Bois, Ibrahim Hur
RIO: ROB-Centric In-Order Modeling of Out-of-Order Processors. IEEE Comput. Archit. Lett. 20 (1) (2021)
Sriram Aananthakrishnan, Nesreen K. Ahmed, Vincent Cavé, Marcelo Cintra, Yigit Demir, Kristof Du Bois, Stijn Eyerman, Joshua B. Fryman, Ivan Ganev, Wim Heirman, Hans-Christian Hoppe, Jason Howard, Ibrahim Hur, Midhunchandra Kodiyath, Samkit Jain, Daniel S. Klowden, Marek M. Landowski, Laurent Montigny, Ankit More, Przemyslaw Ossowski, Robert Pawlowski, Nick Pepperling, Fabrizio Petrini, Mariusz Sikora, Balasubramanian Seshasayee, Shaden Smith, Sebastian Szkoda, Sanjaya Tayal, Jesmin Jahan Tithi, Yves Vandriessche, Izajasz P. Wrosz
PIUMA: Programmable Integrated Unified Memory Architecture. CoRR (2020)
Stijn Eyerman, Wim Heirman, Yigit Demir, Kristof Du Bois, Ibrahim Hur
Projecting Performance for PIUMA using Down-Scaled Simulation. HPEC (2020)
Stijn Eyerman, Wim Heirman, Sam Van den Steen, Ibrahim Hur
Breaking In-Order Branch Miss Recovery. IEEE Comput. Archit. Lett. 19 (1) (2020)
Stijn Eyerman, Wim Heirman, Kristof Du Bois, Joshua B. Fryman, Ibrahim Hur
Many-core graph workload analysis. SC (2018)
Stijn Eyerman, Wim Heirman, Kristof Du Bois, Ibrahim Hur
Extending the Performance Analysis Tool Box: Multi-stage CPI Stacks and FLOPS Stacks. ISPASS (2018)
Wim Heirman, Kristof Du Bois, Yves Vandriessche, Stijn Eyerman, Ibrahim Hur
Near-side prefetch throttling: adaptive prefetching for high-performance many-core processors. PACT (2018)
Stijn Eyerman, Wim Heirman, Kristof Du Bois, Ibrahim Hur
Multi-Stage CPI Stacks. IEEE Comput. Archit. Lett. 17 (1) (2018)
Ajeya Naithani, Stijn Eyerman, Lieven Eeckhout
Optimizing Soft Error Reliability Through Scheduling on Heterogeneous Multicore Processors. IEEE Trans. Computers 67 (6) (2018)
Ajeya Naithani, Stijn Eyerman, Lieven Eeckhout
Reliability-Aware Scheduling on Heterogeneous Multicore Processors. HPCA (2017)
Jennifer B. Sartor, Kristof Du Bois, Stijn Eyerman, Lieven Eeckhout
Analyzing the scalability of managed language applications with speedup stacks. ISPASS (2017)
Sander De Pestel, Stijn Eyerman, Lieven Eeckhout
Linear Branch Entropy: Characterizing and Optimizing Branch Behavior in a Micro-Architecture Independent Way. IEEE Trans. Computers 66 (3) (2017)
Almutaz Adileh, Stijn Eyerman, Aamer Jaleel, Lieven Eeckhout
Mind The Power Holes: Sifting Operating Points in Power-Limited Heterogeneous Multicores. IEEE Comput. Archit. Lett. 16 (1) (2017)
Josué Feliu, Stijn Eyerman, Julio Sahuquillo, Salvador Petit, Lieven Eeckhout
Improving IBM POWER8 Performance Through Symbiotic Job Scheduling. IEEE Trans. Parallel Distributed Syst. 28 (10) (2017)
Ancy Sarah Tom, Narayanan Sundaram, Nesreen K. Ahmed, Shaden Smith, Stijn Eyerman, Midhunchandra Kodiyath, Ibrahim Hur, Fabrizio Petrini, George Karypis
Exploring optimizations on shared-memory platforms for parallel triangle counting algorithms. HPEC (2017)
Sam Van den Steen, Stijn Eyerman, Sander De Pestel, Moncef Mechri, Trevor E. Carlson, David Black-Schaffer, Erik Hagersten, Lieven Eeckhout
Analytical Processor Performance and Power Modeling Using Micro-Architecture Independent Characteristics. IEEE Trans. Computers 65 (12) (2016)
Almutaz Adileh, Stijn Eyerman, Aamer Jaleel, Lieven Eeckhout
Maximizing Heterogeneous Processor Performance Under Power Constraints. ACM Trans. Archit. Code Optim. 13 (3) (2016)
Josué Feliu, Stijn Eyerman, Julio Sahuquillo, Salvador Petit
Symbiotic job scheduling on the IBM POWER8. HPCA (2016)
Stijn Eyerman, Pierre Michaud, Wouter Rogiest
Revisiting symbiotic job scheduling. ISPASS (2015)
Arun Arvind Nair, Stijn Eyerman, Jian Chen, Lizy Kurian John, Lieven Eeckhout
Mechanistic Modeling of Architectural Vulnerability Factor. ACM Trans. Comput. Syst. 32 (4) (2015)
Sam Van den Steen, Sander De Pestel, Moncef Mechri, Stijn Eyerman, Trevor E. Carlson, David Black-Schaffer, Erik Hagersten, Lieven Eeckhout
Micro-architecture independent analytical processor performance and power modeling. ISPASS (2015)
Sander De Pestel, Stijn Eyerman, Lieven Eeckhout
Micro-architecture independent branch behavior characterization. ISPASS (2015)
Stijn Eyerman, Lieven Eeckhout
The benefit of SMT in the multi-core era: flexibility towards degrees of thread-level parallelism. ASPLOS (2014)
Trevor E. Carlson, Wim Heirman, Stijn Eyerman, Ibrahim Hur, Lieven Eeckhout
An Evaluation of High-Level Mechanistic Core Models. ACM Trans. Archit. Code Optim. 11 (3) (2014)
Stijn Eyerman, Lieven Eeckhout
Restating the Case for Weighted-IPC Metrics to Evaluate Multiprogram Workload Performance. IEEE Comput. Archit. Lett. 13 (2) (2014)
Stijn Eyerman, Pierre Michaud, Wouter Rogiest
Multiprogram Throughput Metrics: A Systematic Approach. ACM Trans. Archit. Code Optim. 11 (3) (2014)
Maximilien Breughe, Stijn Eyerman, Lieven Eeckhout
Mechanistic Analytical Modeling of Superscalar In-Order Processor Performance. ACM Trans. Archit. Code Optim. 11 (4) (2014)
Kristof Du Bois, Stijn Eyerman, Jennifer B. Sartor, Lieven Eeckhout
Criticality stacks: identifying critical threads in parallel programs using synchronization behavior. ISCA (2013)
Kristof Du Bois, Jennifer B. Sartor, Stijn Eyerman, Lieven Eeckhout
Bottle graphs: visualizing scalability bottlenecks in multi-threaded applications. OOPSLA (2013)
Kristof Du Bois, Stijn Eyerman, Lieven Eeckhout
Per-thread cycle accounting in multicore processors. ACM Trans. Archit. Code Optim. 9 (4) (2013)
Stijn Eyerman, Kristof Du Bois, Lieven Eeckhout
Speedup stacks: Identifying scaling bottlenecks in multi-threaded applications. ISPASS (2012)
Stijn Eyerman, Lieven Eeckhout
Probabilistic modeling for job symbiosis scheduling on SMT processors. ACM Trans. Archit. Code Optim. 9 (2) (2012)
Arun A. Nair, Stijn Eyerman, Lieven Eeckhout, Lizy Kurian John
A first-order mechanistic model for architectural vulnerability factor. ISCA (2012)
Osman Allam, Stijn Eyerman, Lieven Eeckhout
An efficient CPI stack counter architecture for superscalar processors. ACM Great Lakes Symposium on VLSI (2012)
Maximilien Breughe, Stijn Eyerman, Lieven Eeckhout
A mechanistic performance model for superscalar in-order processors. ISPASS (2012)
Stijn Eyerman, Kenneth Hoste, Lieven Eeckhout
Mechanistic-empirical processor performance modeling for constructing CPI stacks on real hardware. ISPASS (2011)
Maximilien Breughe, Zheng Li, Yang Chen, Stijn Eyerman, Olivier Temam, Chengyong Wu, Lieven Eeckhout
How sensitive is processor customization to the workload's input datasets? SASP (2011)
Stijn Eyerman, Lieven Eeckhout
Fine-grained DVFS using on-chip regulators. ACM Trans. Archit. Code Optim. 8 (1) (2011)
Stijn Eyerman, Lieven Eeckhout
Per-Thread Cycle Accounting. IEEE Micro 30 (1) (2010)
Stijn Eyerman, Lieven Eeckhout
Modeling critical sections in Amdahl's law and its implications for multicore design. ISCA (2010)
Davy Genbrugge, Stijn Eyerman, Lieven Eeckhout
Interval simulation: Raising the level of abstraction in architectural simulation. HPCA (2010)
Stijn Eyerman, Lieven Eeckhout
Probabilistic job symbiosis modeling for SMT processor scheduling. ASPLOS (2010)
Stijn Eyerman, Lieven Eeckhout
A Counter Architecture for Online DVFS Profitability Estimation. IEEE Trans. Computers 59 (11) (2010)
Stijn Eyerman, Lieven Eeckhout
Per-thread cycle accounting in SMT processors. ASPLOS (2009)
Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith
A mechanistic performance model for superscalar out-of-order processors. ACM Trans. Comput. Syst. 27 (2) (2009)
Kenzo Van Craeynest, Stijn Eyerman, Lieven Eeckhout
MLP-Aware Runahead Threads in a Simultaneous Multithreading Processor. HiPEAC (2009)
Stijn Eyerman, Lieven Eeckhout
Memory-level parallelism aware fetch policies for simultaneous multithreading processors. ACM Trans. Archit. Code Optim. 6 (1) (2009)
Stijn Eyerman, Lieven Eeckhout
System-Level Performance Metrics for Multiprogram Workloads. IEEE Micro 28 (3) (2008)
Stijn Eyerman, Lieven Eeckhout, James E. Smith
Studying Compiler Optimizations on Superscalar Processors Through Interval Analysis. HiPEAC (2008)
Stijn Eyerman, Lieven Eeckhout, James E. Smith
Studying Compiler-Microarchitecture Interactions through Interval Analysis. PACT (2007)
Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith
A Top-Down Approach to Architecting CPI Component Performance Counters. IEEE Micro 27 (1) (2007)
Stijn Eyerman, Lieven Eeckhout
A Memory-Level Parallelism Aware Fetch Policy for SMT Processors. HPCA (2007)
Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith
A performance counter architecture for computing accurate CPI components. ASPLOS (2006)
Stijn Eyerman, Lieven Eeckhout, Koen De Bosschere
Efficient design space exploration of high performance embedded out-of-order processors. DATE (2006)
Stijn Eyerman, James E. Smith, Lieven Eeckhout
Characterizing the branch misprediction penalty. ISPASS (2006)