Mechanistic-empirical processor performance modeling for constructing CPI stacks on real hardware.
Stijn EyermanKenneth HosteLieven EeckhoutPublished in: ISPASS (2011)
Keyphrases
- single chip
- real time
- low cost
- high speed
- parallel architectures
- parallel processing
- data sets
- ibm zenterprise
- instruction set
- multi core processors
- high end
- computing systems
- hardware and software
- real life
- image processing
- real world
- hardware implementation
- computer architecture
- computing power
- efficient implementation
- parallel processors
- theoretical analysis
- memory management
- industry standard
- general purpose processors