Wim Heirman

Publication Activity (10 Years)

Years Active: 2005-2024
Publications (10 Years): 23

Top Topics

Multicore Processors

Top Venues

IEEE Comput. Archit. Lett.

ACM Trans. Archit. Code Optim.

Publications

Stijn Eyerman, Wim Heirman, Kristof Du Bois, Ibrahim Hur
Accurate and Scalable Many-Node Simulation. CoRR (2024)
Wim Heirman, Stijn Eyerman
Message from the Program Chairs; ISPASS 2024. ISPASS (2024)
Sriram Aananthakrishnan, Shamsul Abedin, Vincent Cavé, Fabio Checconi, Kristof Du Bois, Stijn Eyerman, Joshua B. Fryman, Wim Heirman, Jason Howard, Ibrahim Hur, Samkit Jain, Marek M. Landowski, Kevin Ma, Jarrod A. Nelson, Robert Pawlowski, Fabrizio Petrini, Sebastian Szkoda, Sanjaya Tayal, Jesmin Jahan Tithi, Yves Vandriessche
The Intel Programmable and Integrated Unified Memory Architecture Graph Analytics Processor. IEEE Micro 43 (5) (2023)
Stijn Eyerman, Sam Van den Steen, Wim Heirman, Ibrahim Hur
Simulating Wrong-Path Instructions in Decoupled Functional-First Simulation. ISPASS (2023)
Alen Sabu, Harish Patil, Wim Heirman, Trevor E. Carlson
LoopPoint: Checkpoint-driven Sampled Simulation for Multi-threaded Applications. HPCA (2022)
Stijn Eyerman, Wim Heirman, Ibrahim Hur
DRAM Bandwidth and Latency Stacks: Visualizing DRAM Bottlenecks. ISPASS (2022)
Wenjie Liu, Wim Heirman, Stijn Eyerman, Shoaib Akram, Lieven Eeckhout
Scale-Model Architectural Simulation. ISPASS (2022)
Stijn Eyerman, Wim Heirman, Sam Van den Steen, Ibrahim Hur
Enabling Branch-Mispredict Level Parallelism by Selectively Flushing Instructions. MICRO (2021)
Wenjie Liu, Wim Heirman, Stijn Eyerman, Shoaib Akram, Lieven Eeckhout
Scale-Model Simulation. IEEE Comput. Archit. Lett. 20 (2) (2021)
Stijn Eyerman, Wim Heirman, Ibrahim Hur
Modeling DRAM Timing in Parallel Simulators With Immediate-Response Memory Model. IEEE Comput. Archit. Lett. 20 (2) (2021)
Harish Patil, Alexander Isaev, Wim Heirman, Alen Sabu, Ali Hajiabadi, Trevor E. Carlson
ELFies: Executable Region Checkpoints for Performance Analysis and Simulation. CGO (2021)
Wim Heirman, Stijn Eyerman, Kristof Du Bois, Ibrahim Hur
Automatic Sublining for Efficient Sparse Memory Accesses. ACM Trans. Archit. Code Optim. 18 (3) (2021)
Wim Heirman, Stijn Eyerman, Kristof Du Bois, Ibrahim Hur
RIO: ROB-Centric In-Order Modeling of Out-of-Order Processors. IEEE Comput. Archit. Lett. 20 (1) (2021)
Sriram Aananthakrishnan, Nesreen K. Ahmed, Vincent Cavé, Marcelo Cintra, Yigit Demir, Kristof Du Bois, Stijn Eyerman, Joshua B. Fryman, Ivan Ganev, Wim Heirman, Hans-Christian Hoppe, Jason Howard, Ibrahim Hur, Midhunchandra Kodiyath, Samkit Jain, Daniel S. Klowden, Marek M. Landowski, Laurent Montigny, Ankit More, Przemyslaw Ossowski, Robert Pawlowski, Nick Pepperling, Fabrizio Petrini, Mariusz Sikora, Balasubramanian Seshasayee, Shaden Smith, Sebastian Szkoda, Sanjaya Tayal, Jesmin Jahan Tithi, Yves Vandriessche, Izajasz P. Wrosz
PIUMA: Programmable Integrated Unified Memory Architecture. CoRR (2020)
Stijn Eyerman, Wim Heirman, Yigit Demir, Kristof Du Bois, Ibrahim Hur
Projecting Performance for PIUMA using Down-Scaled Simulation. HPEC (2020)
Stijn Eyerman, Wim Heirman, Sam Van den Steen, Ibrahim Hur
Breaking In-Order Branch Miss Recovery. IEEE Comput. Archit. Lett. 19 (1) (2020)
Stijn Eyerman, Wim Heirman, Kristof Du Bois, Joshua B. Fryman, Ibrahim Hur
Many-core graph workload analysis. SC (2018)
Stijn Eyerman, Wim Heirman, Kristof Du Bois, Ibrahim Hur
Extending the Performance Analysis Tool Box: Multi-stage CPI Stacks and FLOPS Stacks. ISPASS (2018)
Wim Heirman, Kristof Du Bois, Yves Vandriessche, Stijn Eyerman, Ibrahim Hur
Near-side prefetch throttling: adaptive prefetching for high-performance many-core processors. PACT (2018)
Stijn Eyerman, Wim Heirman, Kristof Du Bois, Ibrahim Hur
Multi-Stage CPI Stacks. IEEE Comput. Archit. Lett. 17 (1) (2018)
Sudhanshu Shekhar Jha, Wim Heirman, Ayose Falcón, Jordi Tubella, Antonio González, Lieven Eeckhout
Shared resource aware scheduling on power-constrained tiled many-core processors. J. Parallel Distributed Comput. 100 (2017)
Sudhanshu Shekhar Jha, Wim Heirman, Ayose Falcón, Jordi Tubella, Antonio González, Lieven Eeckhout
Shared resource aware scheduling on power-constrained tiled many-core processors. Conf. Computing Frontiers (2016)
Shoaib Akram, Jennifer B. Sartor, Kenzo Van Craeynest, Wim Heirman, Lieven Eeckhout
Boosting the Priority of Garbage: Scheduling Collection on Heterogeneous Multicore Processors. ACM Trans. Archit. Code Optim. 13 (1) (2016)
Trevor E. Carlson, Wim Heirman, Osman Allam, Stefanos Kaxiras, Lieven Eeckhout
The load slice core microarchitecture. ISCA (2015)
Sudhanshu Shekhar Jha, Wim Heirman, Ayose Falcón, Trevor E. Carlson, Kenzo Van Craeynest, Jordi Tubella, Antonio González, Lieven Eeckhout
Chrysso: an integrated power manager for constrained many-core processors. Conf. Computing Frontiers (2015)
Trevor E. Carlson, Siddharth Nilakantan, Mark Hempstead, Wim Heirman
Epoch Profiles: Microarchitecture-Based Application Analysis and Optimization. IEEE Comput. Archit. Lett. 14 (1) (2015)
Trevor E. Carlson, Wim Heirman, Kenzo Van Craeynest, Lieven Eeckhout
BarrierPoint: Sampled simulation of multi-threaded applications. ISPASS (2014)
Wim Heirman, Trevor E. Carlson, Kenzo Van Craeynest, Ibrahim Hur, Aamer Jaleel, Lieven Eeckhout
Undersubscribed threading on clustered cache architectures. HPCA (2014)
Trevor E. Carlson, Wim Heirman, Stijn Eyerman, Ibrahim Hur, Lieven Eeckhout
An Evaluation of High-Level Mechanistic Core Models. ACM Trans. Archit. Code Optim. 11 (3) (2014)
Jennifer B. Sartor, Wim Heirman, Stephen M. Blackburn, Lieven Eeckhout, Kathryn S. McKinley
Cooperative cache scrubbing. PACT (2014)
Wim Heirman, Trevor E. Carlson, Kenzo Van Craeynest, Ibrahim Hur, Aamer Jaleel, Lieven Eeckhout
Automatic SMT threading for OpenMP applications on the Intel Xeon Phi co-processor. ROSS@ICS (2014)
Trevor E. Carlson, Wim Heirman, Kenzo Van Craeynest, Lieven Eeckhout
Node Performance and Energy Analysis with the Sniper Multi-core Simulator. Parallel Tools Workshop (2013)
Poona Bahrebar, Ruxandra-Marina Florea, Wim Heirman, Leon Denis, Adrian Munteanu, Dirk Stroobandt
Making Communication a First-Class Citizen in Multicore Partitioning. PDP (2013)
Kenzo Van Craeynest, Shoaib Akram, Wim Heirman, Aamer Jaleel, Lieven Eeckhout
Fairness-aware scheduling on single-ISA heterogeneous multi-cores. PACT (2013)
Chuntao Jiang, Zhibin Yu, Hai Jin, Cheng-Zhong Xu, Lieven Eeckhout, Wim Heirman, Trevor E. Carlson, Xiaofei Liao
PCantorSim: Accelerating parallel architecture simulation through fractal-based sampling. ACM Trans. Archit. Code Optim. 10 (4) (2013)
Trevor E. Carlson, Wim Heirman, Lieven Eeckhout
Sampled simulation of multi-threaded applications. ISPASS (2013)
Wim Heirman, Souradip Sarkar, Trevor E. Carlson, Ibrahim Hur, Lieven Eeckhout
Power-aware multi-core simulation for early design stage hardware/software co-optimization. PACT (2012)
Thomas J. Ashby, Pieter Ghysels, Wim Heirman, Wim Vanroose
The Impact of Global Communication Latency at Extreme Scales on Krylov Methods. ICA3PP (1) (2012)
Wim Heirman, Trevor E. Carlson, Souradip Sarkar, Pieter Ghysels, Wim Vanroose, Lieven Eeckhout
Using Fast and Accurate Simulation to Explore Hardware/Software Trade-offs in the Multi-Core Era. PARCO (2011)
Wim Heirman, Trevor E. Carlson, Shuai Che, Kevin Skadron, Lieven Eeckhout
Using cycle stacks to understand scaling bottlenecks in multi-threaded workloads. IISWC (2011)
Karel Bruneel, Wim Heirman, Dirk Stroobandt
Dynamic data folding with parameterizable FPGA configurations. ACM Trans. Design Autom. Electr. Syst. 16 (4) (2011)
Trevor E. Carlson, Wim Heirman, Lieven Eeckhout
Sniper: exploring the level of abstraction for scalable and accurate parallel multi-core simulation. SC (2011)
Robbe Vancayseele, Brahim Al Farisi, Wim Heirman, Karel Bruneel, Dirk Stroobandt
RecoNoC: A reconfigurable network-on-chip. ReCoSoC (2011)
Zhe Ma, Trevor E. Carlson, Wim Heirman, Lieven Eeckhout
Evaluating Application Vulnerability to Soft Errors in Multi-level Cache Hierarchy. Euro-Par Workshops (2) (2011)
Atef Allam, Ian O'Connor, Wim Heirman
Performance evaluation for passive-type Optical network-on-chip. International Symposium on Rapid System Prototyping (2010)
Wim Heirman, Dirk Stroobandt, Narasinga Rao Miniskar, Roel Wuyts, Francky Catthoor
PinComm: Characterizing Intra-application Communication for the Many-Core Era. ICPADS (2010)
Iñigo Artundo, Wim Heirman, Mikel Loperena, Christof Debaes, Jan M. Van Campenhout, Hugo Thienpont
Low-Power Reconfigurable Network Architecture for On-Chip Photonic Interconnects. Hot Interconnects (2009)
Peter Bertels, Wim Heirman, Dirk Stroobandt
Strategies for dynamic memory allocation in hybrid architectures. Conf. Computing Frontiers (2009)
Peter Bertels, Wim Heirman, Erik H. D'Hollander, Dirk Stroobandt
Efficient memory management for hardware accelerated Java Virtual Machines. ACM Trans. Design Autom. Electr. Syst. 14 (4) (2009)
Peter Bertels, Wim Heirman, Dirk Stroobandt
Efficient measurement of data flow enabling communication-aware parallelisation. IFMT (2008)
Wim Heirman, Joni Dambre, Dirk Stroobandt, Jan M. Van Campenhout
Rent's rule and parallel programs: characterizing network traffic behavior. SLIP (2008)
Wim Heirman, Joni Dambre, Iñigo Artundo, Christof Debaes, Hugo Thienpont, Dirk Stroobandt, Jan Van Campenhout
Predicting the performance of reconfigurable optical interconnects in distributed shared-memory systems. Photonic Netw. Commun. 15 (1) (2008)
Wim Heirman, Joni Dambre, Iñigo Artundo, Christof Debaes, Hugo Thienpont, Dirk Stroobandt, Jan M. Van Campenhout
Predicting reconfigurable interconnect performance in distributed shared-memory systems. Integr. 40 (4) (2007)
Wim Heirman, Joni Dambre, Jan Van Campenhout
Synthetic traffic generation as a tool for dynamic interconnect evaluation. SLIP (2007)
Wim Heirman, Joni Dambre, Jan M. Van Campenhout
Congestion modeling for reconfigurable inter-processor networks. SLIP (2006)
Iñigo Artundo, Daniel Manjarres, Wim Heirman, Christof Debaes, Joni Dambre, Jan M. Van Campenhout, Hugo Thienpont
Reconfigurable Interconnects in DSM Systems: A Focus on Context Switch Behavior. ISPA Workshops (2006)
Wim Heirman, Joni Dambre, Christof Debaes, Hugo Thienpont, Dirk Stroobandt, Jan Van Campenhout
Prediction model for evaluation of reconfigurable interconnects in distributed shared-memory systems. SLIP (2005)
Wim Heirman, Joni Dambre, Jan Van Campenhout, Christof Debaes, Hugo Thienpont
Traffic Temporal Analysis for Reconfigurable Interconnects in Shared-Memory Systems. IPDPS (2005)