Souradip Sarkar

Publication Activity (10 Years)

Years Active: 2007-2019
Publications (10 Years): 3

Top Topics

Reconfigurable Architecture

Nested Transactions

Phylogenetic Trees

Top Venues

IEEE Trans. Computers

Publications

Souradip Sarkar, Purushotham Murugappa, Manil Dev Gomony
A Reconfigurable Architecture for Posit Arithmetic. DSD (2019)
Souradip Sarkar, Manil Dev Gomony
Quater-imaginary base for complex number arithmetic circuits. DATE (2018)
Fabio Pianese, Matteo Signorini, Souradip Sarkar
Small Transactions with Sustainable Incentives. NTMS (2018)
Turbo Majumder, Souradip Sarkar, Partha Pratim Pande, Ananth Kalyanaraman
NoC-Based Hardware Accelerator for Breakpoint Phylogeny. IEEE Trans. Computers 61 (6) (2012)
Wim Heirman, Souradip Sarkar, Trevor E. Carlson, Ibrahim Hur, Lieven Eeckhout
Power-aware multi-core simulation for early design stage hardware/software co-optimization. PACT (2012)
Wim Heirman, Trevor E. Carlson, Souradip Sarkar, Pieter Ghysels, Wim Vanroose, Lieven Eeckhout
Using Fast and Accurate Simulation to Explore Hardware/Software Trade-offs in the Multi-Core Era. PARCO (2011)
Souradip Sarkar, Turbo Majumder, Ananth Kalyanaraman, Partha Pratim Pande
Hardware accelerators for biocomputing: A survey. ISCAS (2010)
Souradip Sarkar, Gaurav Ramesh Kulkarni, Partha Pratim Pande, Ananth Kalyanaraman
Network-on-Chip Hardware Accelerators for Biological Sequence Alignment. IEEE Trans. Computers 59 (1) (2010)
Turbo Majumder, Souradip Sarkar, Partha Pratim Pande, Ananth Kalyanaraman
An optimized NoC architecture for accelerating TSP kernels in breakpoint median problem. ASAP (2010)
Jabulani Nyathi, Souradip Sarkar, Partha Pratim Pande
Multiple clock domain synchronization for network on chip architectures. SoCC (2007)