Purushotham Murugappa

Publication Activity (10 Years)

Years Active: 2011-2019
Publications (10 Years): 2

Top Topics

Dynamic Reconfiguration

Distributed Source Coding

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Souradip Sarkar, Purushotham Murugappa, Manil Dev Gomony
A Reconfigurable Architecture for Posit Arithmetic. DSD (2019)
Vianney Lapotre, Purushotham Murugappa, Guy Gogniat, Amer Baghdadi, Michael Hübner, Jean-Philippe Diguet
A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding. IEEE Trans. Very Large Scale Integr. Syst. 24 (1) (2016)
Vianney Lapotre, Purushotham Murugappa, Guy Gogniat, Amer Baghdadi, Jean-Philippe Diguet, Jean-Noel Bazin, Michael Hübner
A reconfigurable multi-standard ASIP-based turbo decoder for an efficient dynamic reconfiguration in a multi-ASIP context. ISVLSI (2013)
Purushotham Murugappa, Vianney Lapotre, Amer Baghdadi, Michel Jézéquel
Rapid design and prototyping of a reconfigurable decoder architecture for QC-LDPC codes. RSP (2013)
Vianney Lapotre, Michael Hübner, Guy Gogniat, Purushotham Murugappa, Amer Baghdadi, Jean-Philippe Diguet
An efficient on-chip configuration infrastructure for a flexible multi-ASIP turbo decoder architecture. ReCoSoC (2013)
Vianney Lapotre, Purushotham Murugappa, Guy Gogniat, Amer Baghdadi, Jean-Philippe Diguet, Jean-Noel Bazin, Michael Hübner
Optimizations for an efficient reconfiguration of an ASIP-based turbo decoder. ISCAS (2013)
Vianney Lapotre, Purushotham Murugappa, Guy Gogniat, Amer Baghdadi, Michael Hübner, Jean-Philippe Diguet
Stopping-Free Dynamic Configuration of a Multi-ASIP Turbo Decoder. DSD (2013)
Purushotham Murugappa, Amer Baghdadi, Michel Jézéquel
Parameterized area-efficient multi-standard turbo decoder. DATE (2013)
Purushotham Murugappa, Jean-Noel Bazin, Amer Baghdadi, Michel Jézéquel
FPGA prototyping and performance evaluation of multi-standard Turbo/LDPC Encoding and Decoding. RSP (2012)
Rachid Al-Khayat, Purushotham Murugappa, Amer Baghdadi, Michel Jézéquel
Area and throughput optimized ASIP for multi-standard turbo decoding. International Symposium on Rapid System Prototyping (2011)
Purushotham Murugappa, Rachid Al-Khayat, Amer Baghdadi, Michel Jézéquel
A flexible high throughput multi-ASIP architecture for LDPC and turbo decoding. DATE (2011)