Amer Baghdadi

ORCID

Publication Activity (10 Years)

Years Active: 2000-2023
Publications (10 Years): 43

Top Venues

RSP

IEEE Trans. Very Large Scale Integr. Syst.

IEEE Trans. Circuits Syst. II Express Briefs

J. Circuits Syst. Comput.

Grenoble Institute of Technology, France (PHD)

Education History

Grenoble Institute of Technology, France

PHD

Publications

Fatima Hamdar, Jérémy Nadal, Charbel Abdel Nour, Amer Baghdadi
Novel transmission technique based on intentional overlapping for spectral efficiency enhancement in multicarrier systems. PIMRC (2023)
Oualid Mouhoubi, Charbel Abdel Nour, Amer Baghdadi
Latency and Complexity Analysis of Flexible Semi-Parallel Decoding Architectures for 5G NR Polar Codes. IEEE Access 10 (2022)
Dominique Heller, Mostafa Rizk, R. Douguet, Amer Baghdadi, Jean-Philippe Diguet
Marine Objects Detection Using Deep Learning on Embedded Edge Devices. RSP (2022)
Z. Ning, Mostafa Rizk, Amer Baghdadi, Jean-Philippe Diguet
Enhancing embedded AI-based object detection using multi-view approach. RSP (2022)
Oualid Mouhoubi, Charbel Abdel Nour, Amer Baghdadi
Low Latency Architecture Design for Decoding 5G NR Polar Codes. DASIP (2022)
Khaled Alhaj Ali, Amer Baghdadi, Elsa Dupraz, Mathieu Léonardon, Mostafa Rizk, Jean-Philippe Diguet
MOL-Based In-Memory Computing of Binary Neural Networks. IEEE Trans. Very Large Scale Integr. Syst. 30 (7) (2022)
Mostafa Rizk, Amer Baghdadi, Michel Jézéquel
A Literature Survey on Algorithms and Hardware Architectures of Max-Log-MAP Demapping. J. Circuits Syst. Comput. 31 (3) (2022)
Fatima Hamdar, Jérémy Nadal, Charbel Abdel Nour, Amer Baghdadi
Overlap-Save FBMC receivers for massive MIMO systems under channel impairments. VTC Spring (2022)
Mostafa Rizk, Fatima Slim, Amer Baghdadi, Jean-Philippe Diguet
Towards Real-Time Human Detection in Maritime Environment Using Embedded Deep Learning. SYSINT (2022)
Mostafa Rizk, Dominique Heller, R. Douguet, Amer Baghdadi, Jean-Philippe Diguet
Optimization of Deep-Learning Detection of Humans in Marine Environment on Edge Devices. ICECS 2022 (2022)
Oualid Mouhoubi, Charbel Abdel Nour, Amer Baghdadi
On the Latency and Complexity of Semi-Parallel Decoding Architectures for 5G NR Polar Codes. ISIVC (2022)
Hugo Le Blevec, Rami Klaimi, Stefan Weithoffer, Charbel Abdel Nour, Amer Baghdadi
Low Complexity Non-binary Turbo Decoding based on the Local-SOVA Algorithm. ISTC (2021)
Mostafa Rizk, Amer Baghdadi, Michel Jézéquel, Youssef Atat, Yasser Mohanna
NISC-Based MIMO MMSE Detector. J. Circuits Syst. Comput. 30 (4) (2021)
Mostafa Rizk, Amer Baghdadi, Michel Jézéquel, Yasser Mohanna, Youssef Atat
No-instruction-set-computer design experience of flexible and efficient architectures for digital communication applications: two case studies on MIMO turbo detection and universal turbo demapping. Des. Autom. Embed. Syst. 25 (1) (2021)
Jérémy Nadal, Amer Baghdadi
Parallel and Flexible 5G LDPC Decoder Architecture Targeting FPGA. IEEE Trans. Very Large Scale Integr. Syst. 29 (6) (2021)
Muhammad Najam-ul-Islam, Muhammad Nauman, Atif Raza Jafri, Jérémy Nadal, Charbel Abdel Nour, Amer Baghdadi
Hardware Implementation of Overlap-Save-Based Fading Channel Emulator. IEEE Trans. Circuits Syst. II Express Briefs 68 (3) (2021)
Khaled Alhaj Ali, Mostafa Rizk, Amer Baghdadi, Jean-Philippe Diguet, Jalal Jomaah, Naoya Onizawa, Takahiro Hanyu
Memristive Computational Memory Using Memristor Overwrite Logic (MOL). IEEE Trans. Very Large Scale Integr. Syst. 28 (11) (2020)
Khaled Alhaj Ali, Mostafa Rizk, Amer Baghdadi, Jean-Philippe Diguet, Jalal Jomaah
Memristor Overwrite Logic (MOL) for Energy-Efficient In-Memory DNN. ISCAS (2020)
Jérémy Nadal, François Leduc-Primeau, Charbel Abdel Nour, Amer Baghdadi
Overlap-Save FBMC Receivers. IEEE Trans. Wirel. Commun. 19 (8) (2020)
Jérémy Nadal, Amer Baghdadi
FPGA based design and prototyping of efficient 5G QC-LDPC channel decoding. RSP (2020)
Khaled Alhaj Ali, Mostafa Rizk, Amer Baghdadi, Jean-Philippe Diguet, Jalal Jomaah
MRL Crossbar-Based Full Adder Design. ICECS (2019)
Mostafa Rizk, Amer Baghdadi, Michel Jézéquel
Computational Complexity Reduction of MMSE-IC MIMO Turbo Detection. J. Circuits Syst. Comput. 28 (13) (2019)
Khaled Alhaj Ali, Mostafa Rizk, Amer Baghdadi, Jean-Philippe Diguet, Jalal Jomaah
Crossbar Memory Architecture Performing Memristor Overwrite Logic. ICECS (2019)
Muhammad Waqas, Atif Raza Jafri, Amer Baghdadi, Muhammad Najam-ul-Islam
Rapid Prototyping of Parameterized Rotated and Cyclic Q Delayed Constellations Demapper. RSP (2018)
Jérémy Nadal, François Leduc-Primeau, Charbel Abdel Nour, Amer Baghdadi
A Block FBMC Receiver Designed for Short Filters. ICC (2018)
Mostafa Rizk, Amer Baghdadi, Michel Jézéquel, Ali Chamas Al Ghouwayel
NISC Design Experience of Flexible Architectures for Digital Communication Applications. ICCA (2018)
Jérémy Nadal, Charbel Abdel Nour, Amer Baghdadi
Novel UF-OFDM Transmitter: Significant Complexity Reduction Without Signal Approximation. IEEE Trans. Veh. Technol. 67 (3) (2018)
Jean-Philippe Diguet, Naoya Onizawa, Mostafa Rizk, Martha Johanna Sepúlveda, Amer Baghdadi, Takahiro Hanyu
Networked Power-Gated MRAMs for Memory-Based Computing. IEEE Trans. Very Large Scale Integr. Syst. 26 (12) (2018)
Jérémy Nadal, Charbel Abdel Nour, Amer Baghdadi
Design and Evaluation of a Novel Short Prototype Filter for FBMC/OQAM Modulation. IEEE Access 6 (2018)
Vianney Lapotre, Guy Gogniat, Amer Baghdadi, Jean-Philippe Diguet
Dynamic configuration management of a multi-standard and multi-mode reconfigurable multi-ASIP architecture for turbo decoding. EURASIP J. Adv. Signal Process. 2017 (2017)
Mostafa Rizk, Amer Baghdadi, Michel Jézéquel, Yasser Mohanna, Youssef Atat
Efficient quantization and fixed-point representation for MIMO turbo-detection and turbo-demapping. EURASIP J. Embed. Syst. 2017 (2017)
Khaled Alhaj Ali, Mostafa Rizk, Amer Baghdadi, Jean-Philippe Diguet, Jalal Jomaah
Towards memristor-based reconfigurable FFT architecture. ICM (2017)
Jérémy Nadal, Charbel Abdel Nour, Amer Baghdadi
Design and Evaluation of a Novel Short Prototype Filter for FBMC/OQAM Modulation. CoRR (2017)
Mostafa Rizk, Jean-Philippe Diguet, Naoya Onizawa, Amer Baghdadi, Martha Johanna Sepúlveda, Y. Akgul, Vincent Gripon, Takahiro Hanyu
NoC-MRAM architecture for memory-based computing: Database-search case study. NEWCAS (2017)
Atif Raza Jafri, Amer Baghdadi, Muhammad Waqas, Muhammad Najam-ul-Islam
High-Throughput and Area-Efficient Rotated and Cyclic Q Delayed Constellations Demapper for Future Wireless Standards. IEEE Access 5 (2017)
Said Medjkouh, Jérémy Nadal, Charbel Abdel Nour, Amer Baghdadi
Reduced complexity FPGA implementation for UF-OFDM frequency domain transmitter. SiPS (2017)
Atif Raza Jafri, Amer Baghdadi, Muhammad Najam-ul-Islam, Michel Jézéquel
Heterogeneous Multi-ASIP and NoC-Based Architecture for Adaptive Parallel TBICM-ID-SSD. IEEE Trans. Circuits Syst. II Express Briefs (3) (2017)
Jérémy Nadal, Charbel Abdel Nour, Amer Baghdadi
Flexible hardware platform for demonstrating new 5G waveform candidates. ICM (2017)
Jérémy Nadal, Charbel Abdel Nour, Amer Baghdadi
Low-Complexity Pipelined Architecture for FBMC/OQAM Transmitter. IEEE Trans. Circuits Syst. II Express Briefs (1) (2016)
Vianney Lapotre, Purushotham Murugappa, Guy Gogniat, Amer Baghdadi, Michael Hübner, Jean-Philippe Diguet
A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding. IEEE Trans. Very Large Scale Integr. Syst. 24 (1) (2016)
Valentin Mena Morales, Yahia Brakni, Pierre-Henri Horrein, Amer Baghdadi
Caasper: providing accessible FPGA-acceleration over the network. RSP (2015)
Carlo Condo, Amer Baghdadi, Guido Masera
Reducing the Dissipated Energy in Multi-standard Turbo and LDPC Decoders. Circuits Syst. Signal Process. 34 (5) (2015)
Mostafa Rizk, Amer Baghdadi, Michel Jézéquel, Yasser Mohanna, Youssef Atat
NISC-Based Soft-Input-Soft-Output Demapper. IEEE Trans. Circuits Syst. II Express Briefs (11) (2015)
Carlo Condo, Amer Baghdadi, Guido Masera
Energy-efficient multi-standard early stopping criterion for low-density-parity-check iterative decoding. IET Commun. 8 (12) (2014)
Valentin Mena Morales, Pierre-Henri Horrein, Amer Baghdadi, Erik Hochapfel, Sandrine Vaton
Energy-efficient FPGA implementation for binomial option pricing using OpenCL. DATE (2014)
Mostafa Rizk, Amer Baghdadi, Michel Jézéquel, Yasser Mohanna, Youssef Atat
Design and prototyping flow of NISC-based flexible MIMO turbo-equalizer. RSP (2014)
Houcine Chougrani, Jean Schwoerer, Pierre-Henri Horrein, Amer Baghdadi, Francois Dehmas
UWB-IR digital baseband architecture for IEEE 802.15.6 wireless BAN. ICECS (2014)
Vianney Lapotre, Purushotham Murugappa, Guy Gogniat, Amer Baghdadi, Jean-Philippe Diguet, Jean-Noel Bazin, Michael Hübner
A reconfigurable multi-standard ASIP-based turbo decoder for an efficient dynamic reconfiguration in a multi-ASIP context. ISVLSI (2013)
Purushotham Murugappa, Vianney Lapotre, Amer Baghdadi, Michel Jézéquel
Rapid design and prototyping of a reconfigurable decoder architecture for QC-LDPC codes. RSP (2013)
Carlo Condo, Amer Baghdadi, Guido Masera
A Joint Communication and Application Simulator for NoC-Based Custom SoCs: LDPC and Turbo Codes Parallel Decoding Case Study. DSD (2013)
Mostafa Rizk, Amer Baghdadi, Michel Jézéquel, Yasser Mohanna, Youssef Atat
Flexible and efficient architecture design for MIMO MMSE-IC linear turbo-equalization. ICCIT (2013)
Vianney Lapotre, Michael Hübner, Guy Gogniat, Purushotham Murugappa, Amer Baghdadi, Jean-Philippe Diguet
An efficient on-chip configuration infrastructure for a flexible multi-ASIP turbo decoder architecture. ReCoSoC (2013)
Mostafa Rizk, Amer Baghdadi, Michel Jézéquel, Yasser Mohana, Youssef Atat
Statically-scheduled application-specific processor design: a case-study on MMSE MIMO equalization. DATE (2013)
Vianney Lapotre, Purushotham Murugappa, Guy Gogniat, Amer Baghdadi, Jean-Philippe Diguet, Jean-Noel Bazin, Michael Hübner
Optimizations for an efficient reconfiguration of an ASIP-based turbo decoder. ISCAS (2013)
Vianney Lapotre, Purushotham Murugappa, Guy Gogniat, Amer Baghdadi, Michael Hübner, Jean-Philippe Diguet
Stopping-Free Dynamic Configuration of a Multi-ASIP Turbo Decoder. DSD (2013)
Purushotham Murugappa, Amer Baghdadi, Michel Jézéquel
Parameterized area-efficient multi-standard turbo decoder. DATE (2013)
Salim Haddad, Amer Baghdadi, Michel Jézéquel
Complexity adaptive iterative receiver performing TBICM-ID-SSD. EURASIP J. Adv. Signal Process. 2012 (2012)
Rachid Al-Khayat, Amer Baghdadi, Michel Jézéquel
multi-standard turbo decoder. ISSoC (2012)
Vianney Lapotre, Guy Gogniat, Jean-Philippe Diguet, Salim Haddad, Amer Baghdadi
An analytical approach for sizing of heterogeneous multiprocessor flexible platforms for iterative demapping and channel decoding. ReConFig (2012)
Purushotham Murugappa, Jean-Noel Bazin, Amer Baghdadi, Michel Jézéquel
FPGA prototyping and performance evaluation of multi-standard Turbo/LDPC Encoding and Decoding. RSP (2012)
Salim Haddad, Amer Baghdadi, Michel Jézéquel
On the Convergence Speed of Turbo Demodulation With Turbo Decoding. IEEE Trans. Signal Process. 60 (8) (2012)
Guido Masera, Amer Baghdadi, Frank Kienle, Christophe Moy
Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation. VLSI Design 2012 (2012)
Salim Haddad, Oscar Sanchez, Amer Baghdadi, Michel Jézéquel
Complexity reduction of shuffled parallel iterative demodulation with turbo decoding. ICT (2012)
Salim Haddad, Amer Baghdadi, Michel Jézéquel
On the Convergence Speed of Turbo Demodulation with Turbo Decoding CoRR (2012)
Salim Haddad, Amer Baghdadi, Michel Jézéquel
Adaptive complexity MIMO turbo receiver applying turbo demodulation. ISTC (2012)
Atif Raza Jafri, Amer Baghdadi, Michel Jézéquel
Parallel MIMO Turbo Equalization. IEEE Commun. Lett. 15 (3) (2011)
Salim Haddad, Amer Baghdadi, Michel Jézéquel
Reducing the number of iterations in iterative demodulation with turbo decoding. SoftCOM (2011)
Pallavi Reddy, Fabien Clermidy, Amer Baghdadi, Michel Jézéquel
A low complexity stopping criterion for reducing power consumption in turbo decoders. DATE (2011)
Rachid Al-Khayat, Purushotham Murugappa, Amer Baghdadi, Michel Jézéquel
Area and throughput optimized ASIP for multi-standard turbo decoding. International Symposium on Rapid System Prototyping (2011)
Purushotham Murugappa, Rachid Al-Khayat, Amer Baghdadi, Michel Jézéquel
A flexible high throughput multi-ASIP architecture for LDPC and turbo decoding. DATE (2011)
Maurizio Martina, Guido Masera, Hazem Moussa, Amer Baghdadi
On chip interconnects for multiprocessor turbo decoding architectures. Microprocess. Microsystems 35 (2) (2011)
Pallavi Reddy, Fabien Clermidy, Rasheed Al Khayat, Amer Baghdadi, Michel Jézéquel
Power consumption analysis and energy efficient optimization for turbo decoder implementation. SoC (2010)
Olivier Muller, Amer Baghdadi, Michel Jézéquel
Parallelism Efficiency in Convolutional Turbo Decoding. EURASIP J. Adv. Signal Process. 2010 (2010)
Atif Raza Jafri, Amer Baghdadi, Michel Jézéquel
Rapid design and prototyping of universal soft demapper. ISCAS (2010)
Fabrizio Vacca, Guido Masera, Hazem Moussa, Amer Baghdadi, Michel Jézéquel
Flexible Architectures for LDPC Decoders Based on Network on Chip Paradigm. DSD (2009)
Jean Saad, Amer Baghdadi, Frantz Bodereau
FPGA-based Radar Signal Processing for Automotive Driver Assistance System. IEEE International Workshop on Rapid System Prototyping (2009)
Olivier Muller, Amer Baghdadi, Michel Jézéquel
From Parallelism Levels to a Multi-ASIP Architecture for Turbo Decoding. IEEE Trans. Very Large Scale Integr. Syst. 17 (1) (2009)
Atif Raza Jafri, Amer Baghdadi, Michel Jézéquel
Rapid Prototyping of ASIP-based Flexible MMSE-IC Linear Equalizer. IEEE International Workshop on Rapid System Prototyping (2009)
Atif Raza Jafri, Amer Baghdadi, Michel Jézéquel
ASIP-Based Universal Demapper for Multiwireless Standards. IEEE Embed. Syst. Lett. 1 (1) (2009)
Chafic Jaber, Andreas Kanstein, Ludovic Apvrille, Amer Baghdadi, Patricia Le Moenner, Renaud Pacalet
High-Level System Modeling for Rapid HW/SW Architecture Exploration. IEEE International Workshop on Rapid System Prototyping (2009)
Atif Raza Jafri, Daoud Karakolah, Amer Baghdadi, Michel Jézéquel
ASIP-based flexible MMSE-IC Linear Equalizer for MIMO turbo-equalization applications. DATE (2009)
Olivier Muller, Amer Baghdadi, Michel Jézéquel
From Application to ASIP-based FPGA Prototype: a Case Study on Turbo Decoding. IEEE International Workshop on Rapid System Prototyping (2008)
Hazem Moussa, Amer Baghdadi, Michel Jézéquel
Binary de Bruijn interconnection network for a flexible LDPC/turbo decoder. ISCAS (2008)
Hazem Moussa, Amer Baghdadi, Michel Jézéquel
Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoder. DAC (2008)
Hazem Moussa, Olivier Muller, Amer Baghdadi, Michel Jézéquel
Butterfly and benes-based on-chip communication networks for multiprocessor turbo decoding. DATE (2007)
Olivier Muller, Amer Baghdadi, Michel Jézéquel
On the Parallelism of Convolutional Turbo Decoding and Interleaving Interference. GLOBECOM (2006)
Olivier Muller, Amer Baghdadi, Michel Jézéquel
ASIP-based multiprocessor SoC design for simple and double binary turbo decoding. DATE (2006)
Nacer-Eddine Zergainoh, Amer Baghdadi, Ahmed Amine Jerraya
Hardware/software codesign of on-chip communication architecture for application-specific multiprocessor system-on-chip. Int. J. Embed. Syst. 1 (1/2) (2005)
Ferid Gharsalli, Amer Baghdadi, Marius Bonaciu, Giedrius Majauskas, Wander O. Cesário, Ahmed Amine Jerraya
An Efficient Architecture for the Implementation of Message Passing Programming Model on Massive Multiprocessor. IEEE International Workshop on Rapid System Prototyping (2004)
Sang-Il Han, Amer Baghdadi, Marius Bonaciu, Soo-Ik Chae, Ahmed Amine Jerraya
An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory. DAC (2004)
Nacer-Eddine Zergainoh, Amer Baghdadi, Ahmed Amine Jerraya
A generic architecture model based-methodology for an efficient design of hardware/software application-specific multiprocessor System-on-Chip. Ann. des Télécommunications 59 (7-8) (2004)
Arif Sasongko, Amer Baghdadi, Frédéric Rousseau, Ahmed Amine Jerraya
Embedded Application Prototyping on a Communication-Restricted Reconfigurable. IEEE International Workshop on Rapid System Prototyping (2003)
Arif Sasongko, Amer Baghdadi, Frédéric Rousseau, Ahmed Amine Jerraya
Towards SoC Validation Through Prototyping: A Systematic Approach Based on Reconfigurable Platform. Des. Autom. Embed. Syst. 8 (2-3) (2003)
Wander O. Cesário, Amer Baghdadi, Lovic Gauthier, Damien Lyonnard, Gabriela Nicolescu, Yanick Paviot, Sungjoo Yoo, Ahmed Amine Jerraya, Mario Diaz-Nava
Component-based design approach for multicore SoCs. DAC (2002)
Amer Baghdadi, Nacer-Eddine Zergainoh, Wander O. Cesário, Ahmed Amine Jerraya
Combining a Performance Estimation Methodology with a Hardware/Software Codesign Flow Supporting Multiprocessor Systems. IEEE Trans. Software Eng. 28 (9) (2002)
Amer Baghdadi, Nacer-Eddine Zergainoh, Wander O. Cesário, Ahmed Amine Jerraya
Exploration de l'espace des solutions architecturales dans le codesign. Tech. Sci. Informatiques 21 (1) (2002)
Damien Lyonnard, Sungjoo Yoo, Amer Baghdadi, Ahmed Amine Jerraya
Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip. DAC (2001)
Sungjoo Yoo, Gabriela Nicolescu, Damien Lyonnard, Amer Baghdadi, Ahmed Amine Jerraya
A generic wrapper architecture for multi-processor SoC cosimulation and design. CODES (2001)
Amer Baghdadi, Damien Lyonnard, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya
An efficient architecture model for systematic design of application-specific multiprocessor SoC. DATE (2001)
Amer Baghdadi, Nacer-Eddine Zergainoh, Damien Lyonnard, Ahmed Amine Jerraya
Generic Architecture Platform for Multiprocessor System-On-Chip Design. DIPES (2000)

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Publication Activity (10 Years)

Top Topics

Top Venues

Amer Baghdadi