Guido Masera

ORCID

Publication Activity (10 Years)

Years Active: 1989-2024
Publications (10 Years): 64

Top Venues

CoRR

IJCNN

ApplePies

IEEE Trans. Circuits Syst. Video Technol.

Publications

Flavia Guella, Emanuele Valpreda, Michele Caon, Guido Masera, Maurizio Martina
MARLIN: A Co-Design Methodology for Approximate ReconfigurabLe Inference of Neural Networks at the Edge. IEEE Trans. Circuits Syst. I Regul. Pap. 71 (5) (2024)
Michele Caon, Vincenzo Petrolo, Mattia Mirigaldi, Flavia Guella, Guido Masera, Maurizio Martina
Seeing Beyond the Order: a LEN5 to Sharpen Edge Microprocessors with Dynamic Scheduling. CF (Companion) (2024)
Alessandra Dolmeta, Emanuele Valpreda, Maurizio Martina, Guido Masera
Implementation and integration of NTT/INTT accelerator on RISC-V for CRYSTALS-Kyber. CF (Companion) (2024)
Eugenio Ressa, Alberto Marchisio, Maurizio Martina, Guido Masera, Muhammad Shafique
TinyCL: An Efficient Hardware Architecture for Continual Learning on Autonomous Systems. CoRR (2024)
Michele Caon, Clément Choné, Pasquale Davide Schiavone, Alexandre Levisse, Guido Masera, Maurizio Martina, David Atienza
Scalable and RISC-V Programmable Near-Memory Computing Architectures for Edge Nodes. CoRR (2024)
Alessandra Dolmeta, Mattia Mirigaldi, Maurizio Martina, Guido Masera
LOKI Low-Latency Open-Source Kyber-Accelerator IPs. ApplePies (2023)
Kristjane Koleci, Paolo Mazzetti, Maurizio Martina, Guido Masera
A Flexible NTT-Based Multiplier for Post-Quantum Cryptography. IEEE Access 11 (2023)
Alessandra Dolmeta, Maurizio Martina, Guido Masera
Hardware architecture for CRYSTALS-Kyber post-quantum cryptographic SHA-3 primitives. PRIME (2023)
Alessandra Dolmeta, Mattia Mirigaldi, Maurizio Martina, Guido Masera
Implementation and integration of Keccak accelerator on RISC-V for CRYSTALS-Kyber. CF (2023)
Fabrizio Ottati, Giovanna Turvani, Marco Vacca, Guido Masera
Custom Memory Design for Logic-in-Memory: Drawbacks and Improvements over Conventional Memories. CoRR (2023)
Alberto Marchisio, Davide Dura, Maurizio Capra, Maurizio Martina, Guido Masera, Muhammad Shafique
SwiftTron: An Efficient Hardware Accelerator for Quantized Transformers. IJCNN (2023)
Alessandra Dolmeta, Maurizio Martina, Guido Masera
Comparative Study of Keccak SHA-3 Implementations. Cryptogr. 7 (4) (2023)
Alberto Marchisio, Davide Dura, Maurizio Capra, Maurizio Martina, Guido Masera, Muhammad Shafique
SwiftTron: An Efficient Hardware Accelerator for Quantized Transformers. CoRR (2023)
Emanuele Valpreda, Giuseppe Palumbo, Michele Caon, Guido Masera, Maurizio Martina
ERODE: Error Resilient Object DetEction by Recovering Bounding Box and Class Information. PRIME (2023)
Simone Favero, Maurizio Martina, Guido Masera
Architectural Comparison Model for Area-Efficient PMAP Turbo-Decoders. IEEE Trans. Circuits Syst. II Express Briefs 70 (1) (2023)
William Fornaciari, Federico Reghenzani, Giovanni Agosta, Davide Zoni, Andrea Galimberti, Francesco Conti, Yvan Tortorella, Emanuele Parisi, Francesco Barchi, Andrea Bartolini, Andrea Acquaviva, Daniele Gregori, Salvatore Cognetta, Carlo Ciancarelli, Antonio Leboffe, Paolo Serri, Alessio Burrello, Daniele Jahier Pagliari, Gianvito Urgese, Maurizio Martina, Guido Masera, Rosario Di Carlo, Antonio Sciarappa
RISC-V Processor Technologies for Aerospace Applications in the ISOLDE Project. SAMOS (2023)
Flavia Guella, Emanuele Valpreda, Michele Caon, Guido Masera, Maurizio Martina
TEMET: Truncated REconfigurable Multiplier with Error Tuning. ApplePies (2023)
Alberto Viale, Alberto Marchisio, Maurizio Martina, Guido Masera, Muhammad Shafique
LaneSNNs: Spiking Neural Networks for Lane Detection on the Loihi Neuromorphic Processor. CoRR (2022)
Alberto Marchisio, Beatrice Bussolino, Edoardo Salvati, Maurizio Martina, Guido Masera, Muhammad Shafique
Enabling Capsule Networks at the Edge through Approximate Softmax and Squash Operations. CoRR (2022)
Alberto Marchisio, Beatrice Bussolino, Edoardo Salvati, Maurizio Martina, Guido Masera, Muhammad Shafique
Enabling Capsule Networks at the Edge through Approximate Softmax and Squash Operations. ISLPED (2022)
Muhammad Abdullah Hanif, Giuseppe Maria Sarda, Alberto Marchisio, Guido Masera, Maurizio Martina, Muhammad Shafique
CoNLoCNN: Exploiting Correlation and Non-Uniform Quantization for Energy-Efficient Low-precision Deep Convolutional Neural Networks. CoRR (2022)
Alberto Viale, Alberto Marchisio, Maurizio Martina, Guido Masera, Muhammad Shafique
LaneSNNs: Spiking Neural Networks for Lane Detection on the Loihi Neuromorphic Processor. IROS (2022)
Kristjane Koleci, Lorenzo Cecchetti, Guido Masera, Maurizio Martina, Massimo Ruo Roch
A Side Channel Attack Methodology Applied to Code-Based Post Quantum Cryptography. ApplePies (2022)
Giuseppe Aiello, Beatrice Bussolino, Emanuele Valpreda, Massimo Ruo Roch, Guido Masera, Maurizio Martina, Stefano Marsi
NLCMAP: A Framework for the Efficient Mapping of Non-Linear Convolutional Neural Networks on FPGA Accelerators. ICIP (2022)
Muhammad Abdullah Hanif, Giuseppe Maria Sarda, Alberto Marchisio, Guido Masera, Maurizio Martina, Muhammad Shafique
CoNLoCNN: Exploiting Correlation and Non-Uniform Quantization for Energy-Efficient Low-precision Deep Convolutional Neural Networks. IJCNN (2022)
Alberto Viale, Alberto Marchisio, Maurizio Martina, Guido Masera, Muhammad Shafique
CarSNN: An Efficient Spiking Neural Network for Event-Based Autonomous Cars on the Loihi Neuromorphic Research Processor. CoRR (2021)
Alberto Viale, Alberto Marchisio, Maurizio Martina, Guido Masera, Muhammad Shafique
CarSNN: An Efficient Spiking Neural Network for Event-Based Autonomous Cars on the Loihi Neuromorphic Research Processor. IJCNN (2021)
Alberto Marchisio, Giacomo Pira, Maurizio Martina, Guido Masera, Muhammad Shafique
DVS-Attacks: Adversarial Attacks on Dynamic Vision Sensors for Spiking Neural Networks. CoRR (2021)
Kristjane Koleci, Paolo Santini, Marco Baldi, Franco Chiaraluce, Maurizio Martina, Guido Masera
Efficient Hardware Implementation of the LEDAcrypt Decoder. IEEE Access 9 (2021)
Alberto Marchisio, Giacomo Pira, Maurizio Martina, Guido Masera, Muhammad Shafique
DVS-Attacks: Adversarial Attacks on Dynamic Vision Sensors for Spiking Neural Networks. IJCNN (2021)
Walid Walid, Muhammad Awais, Ashfaq Ahmed, Guido Masera, Maurizio Martina
Real-time implementation of fast discriminative scale space tracking algorithm. J. Real Time Image Process. 18 (6) (2021)
Alberto Marchisio, Giacomo Pira, Maurizio Martina, Guido Masera, Muhammad Shafique
R-SNN: An Analysis and Design Methodology for Robustifying Spiking Neural Networks against Adversarial Attacks through Noise Filters for Dynamic Vision Sensors. CoRR (2021)
Alberto Marchisio, Giacomo Pira, Maurizio Martina, Guido Masera, Muhammad Shafique
R-SNN: An Analysis and Design Methodology for Robustifying Spiking Neural Networks against Adversarial Attacks through Noise Filters for Dynamic Vision Sensors. IROS (2021)
Jurgen Kello, Massimo Ruo Roch, Guido Masera, Maurizio Martina
Low-Complexity Reconfigurable DCT-V Architecture. IEEE Trans. Circuits Syst. (12) (2020)
Maurizio Capra, Beatrice Bussolino, Alberto Marchisio, Guido Masera, Maurizio Martina, Muhammad Shafique
Hardware and Software Optimizations for Accelerating Deep Neural Networks: Survey of Current Trends, Challenges, and the Road Ahead. IEEE Access 8 (2020)
Maurizio Capra, Beatrice Bussolino, Alberto Marchisio, Muhammad Shafique, Guido Masera, Maurizio Martina
An Updated Survey of Efficient Hardware Architectures for Accelerating Deep Convolutional Neural Networks. Future Internet 12 (7) (2020)
Maurizio Capra, Beatrice Bussolino, Alberto Marchisio, Guido Masera, Maurizio Martina, Muhammad Shafique
Hardware and Software Optimizations for Accelerating Deep Neural Networks: Survey of Current Trends, Challenges, and the Road Ahead. CoRR (2020)
Alessio Colucci, Alberto Marchisio, Beatrice Bussolino, Vojtech Mrazek, Maurizio Martina, Guido Masera, Muhammad Shafique
A Fast Design Space Exploration Framework for the Deep Learning Accelerators: Work-in-Progress. CODES+ISSS (2020)
Maurizio Masera, Guido Masera, Maurizio Martina
An Area-Efficient Variable-Size Fixed-Point DCT Architecture for HEVC Encoding. IEEE Trans. Circuits Syst. Video Technol. 30 (1) (2020)
Kristjane Koleci, Marco Baldi, Maurizio Martina, Guido Masera
A Hardware Implementation for Code-based Post-quantum Asymmetric Cryptography. ITASEC (2020)
Alberto Marchisio, Beatrice Bussolino, Alessio Colucci, Maurizio Martina, Guido Masera, Muhammad Shafique
Q-CapsNets: A Specialized Framework for Quantizing Capsule Networks. DAC (2020)
Alberto Marchisio, Beatrice Bussolino, Alessio Colucci, Maurizio Martina, Guido Masera, Muhammad Shafique
Q-CapsNets: A Specialized Framework for Quantizing Capsule Networks. CoRR (2020)
Riccardo Peloso, Maurizio Capra, Luigi Sole, Massimo Ruo Roch, Guido Masera, Maurizio Martina
Steerable-Discrete-Cosine-Transform (SDCT): Hardware Implementation and Performance Analysis. Sensors 20 (5) (2020)
Alberto Marchisio, Beatrice Bussolino, Alessio Colucci, Muhammad Abdullah Hanif, Maurizio Martina, Guido Masera, Muhammad Shafique
FasTrCaps: An Integrated Framework for Fast yet Accurate Training of Capsule Networks. IJCNN (2020)
Maurizio Capra, Riccardo Peloso, Guido Masera, Massimo Ruo Roch, Maurizio Martina
Edge Computing: A Survey On the Hardware Requirements in the Internet of Things World. Future Internet 11 (4) (2019)
Alberto Marchisio, Beatrice Bussolino, Alessio Colucci, Muhammad Abdullah Hanif, Maurizio Martina, Guido Masera, Muhammad Shafique
X-TrainCaps: Accelerated Training of Capsule Nets through Lightweight Software Optimizations. CoRR (2019)
Luigi Sole, Riccardo Peloso, Maurizio Capra, Massimo Ruo Roch, Guido Masera, Maurizio Martina
VLSI Architectures for the Steerable-Discrete-Cosine-Transform (SDCT). ApplePies (2019)
Muhammad Awais, Anas Razzaq, Ashfaq Ahmed, Guido Masera
LDPC check node implementation using reversible logic. IET Circuits Devices Syst. 13 (4) (2019)
Alberto Paltrinieri, Riccardo Peloso, Guido Masera, Muhammad Shafique, Maurizio Martina
On the Effect of Approximate-Computing in Motion Estimation. J. Low Power Electron. 15 (1) (2019)
Paolo Selvo, Maurizio Masera, Riccardo Peloso, Guido Masera, Muhammad Shafique, Maurizio Martina
An Optimized Partial-Distortion-Elimination Based Sum-of-Absolute-Differences Architecture for High-Efficiency-Video-Coding. ApplePies (2018)
Alberto Paltrinieri, Riccardo Peloso, Guido Masera, Muhammad Shafique, Maurizio Martina
Approximate-Computing Architectures for Motion Estimation in HEVC. NGCAS (2018)
Gabriele Coppolino, Carlo Condo, Guido Masera, Warren J. Gross
Efficient Operation Scheduling in Successive-Cancellation-based polar decoders. SiPS (2018)
Gabriele Coppolino, Carlo Condo, Guido Masera, Warren J. Gross
A Multi-Kernel Multi-Code Polar Decoder Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2018)
Gabriele Coppolino, Carlo Condo, Guido Masera, Warren J. Gross
A Multi-Kernel Multi-Code Polar Decoder Architecture. CoRR (2018)
Erik Anzalone, Maurizio Capra, Riccardo Peloso, Maurizio Martina, Guido Masera
Low-Power Hardware Accelerator for Sparse Matrix Convolution in Deep Neural Network. IIH-MSP (1) (2017)
Maurizio Masera, Lorenzo Re Fiorentin, Enrico Masala, Guido Masera, Maurizio Martina
Analysis of HEVC transform throughput requirements for hardware implementations. Signal Process. Image Commun. 57 (2017)
Giovanni Renda, Maurizio Masera, Maurizio Martina, Guido Masera
Approximate Arai DCT Architecture for HEVC. NGCAS (2017)
Maurizio Masera, Maurizio Martina, Guido Masera
Adaptive Approximated DCT Architectures for HEVC. IEEE Trans. Circuits Syst. Video Technol. 27 (12) (2017)
Maurizio Masera, Maurizio Martina, Guido Masera
Odd type DCT/DST for video coding: Relationships and low-complexity implementations. SiPS (2017)
Simone Aiassa, Paolo Motto Ros, Guido Masera, Maurizio Martina
A low power architecture for AER event-processing microcontroller. BioCAS (2017)
Lorenzo Re Fiorentin, Maurizio Masera, Sabino Mantovano, Paola Sunna, Guido Masera, Maurizio Martina
Comparison between HEVC and Thor based on objective and subjective assessments. IWSSIP (2016)
Syed Azhar Ali Zaidi, Abuduwaili Tuoheti, Maurizio Martina, Guido Masera
FPGA Accelerator of Algebraic Quasi Cyclic LDPC Codes for nand Flash Memories. IEEE Des. Test 33 (6) (2016)
Waqar Ahmad, Javed Iqbal, Maurizio Martina, Guido Masera
High Level Synthesis based FPGA Implementation of H.264/AVC Sub-Pixel Luma Interpolation Filters. EMS (2016)
Lorenzo Guerrieri, Guido Masera, Igor S. Stievano, Paola Bisaglia, Williams Richard Garcia Valverde, Mara Concolato
Automotive Power-Line Communication Channels: Mathematical Characterization and Hardware Emulator. IEEE Trans. Ind. Electron. 63 (5) (2016)
Carlo Condo, Guido Masera, Paolo Montuschi
Unequal Error Protection of Memories in LDPC Decoders. IEEE Trans. Computers 64 (10) (2015)
Carlo Condo, Amer Baghdadi, Guido Masera
Reducing the Dissipated Energy in Multi-standard Turbo and LDPC Decoders. Circuits Syst. Signal Process. 34 (5) (2015)
Muhammad Usman Shahid, Ashfaq Ahmed, Maurizio Martina, Guido Masera, Enrico Magli
Parallel H.264/AVC Fast Rate-Distortion Optimized Motion Estimation by Using a Graphics Processing Unit and Dedicated Hardware. IEEE Trans. Circuits Syst. Video Technol. 25 (4) (2015)
Carlo Condo, Maurizio Martina, Massimo Ruo Roch, Guido Masera
Exploiting generalized de-Bruijn/Kautz topologies for flexible iterative channel code decoder architectures. Integr. 50 (2015)
Maurizio Masera, Lorenzo Re Fiorentin, Maurizio Martina, Guido Masera, Enrico Masala
Optimizing the transform complexity-quality tradeoff for hardware-accelerated HEVC video coding. DASIP (2015)
Masoud Shahshahani Amirhossein, Paolo Motto Ros, Alberto Bonanno, Marco Crepaldi, Maurizio Martina, Danilo Demarchi, Guido Masera
An all-digital spike-based ultra-low-power IR-UWB dynamic average threshold crossing scheme for muscle force wireless transmission. DATE (2015)
Stylianos Papaharalabos, P. Takis Mathiopoulos, Maurizio Martina, Guido Masera
Comments on "Bitwise Log-Likelihood Ratios for Quadrature Amplitude Modulations". IEEE Commun. Lett. 19 (11) (2015)
Waqar Ahmad, Maurizio Martina, Guido Masera
Complexity and implementation analysis of synthesized view distortion estimation architecture in 3D High Efficiency Video Coding. IC3D (2015)
Maurizio Martina, Guido Masera, Massimo Ruo Roch, Gianluca Piccinini
Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2015)
Carlo Condo, Amer Baghdadi, Guido Masera
Energy-efficient multi-standard early stopping criterion for low-density-parity-check iterative decoding. IET Commun. 8 (12) (2014)
Carlo Condo, Maurizio Martina, Massimo Ruo Roch, Guido Masera
Rediscovering Logarithmic Diameter Topologies for Low Latency Network-on-Chip-Based Applications. PDP (2014)
Guoping Xiao, Maurizio Martina, Guido Masera, Gianluca Piccinini
A Parallel Radix-Sort-Based VLSI Architecture for Finding the First W Maximum/Minimum Values. IEEE Trans. Circuits Syst. II Express Briefs (11) (2014)
Simone Zezza, Guido Masera, Saeid Nooshabadi
A novel decoder architecture for error resilient JPEG2000 applications based on MQ arithmetic. ISCAS (2014)
Maurizio Martina, Stylianos Papaharalabos, P. Takis Mathiopoulos, Guido Masera
Simplified Log-MAP Algorithm for Very Low-Complexity Turbo Decoder Hardware Architectures. IEEE Trans. Instrum. Meas. 63 (3) (2014)
Carlo Condo, Guido Masera
Unified turbo/LDPC code decoder architecture for deep-space communications. IEEE Trans. Aerosp. Electron. Syst. 50 (4) (2014)
Maurizio Awais, Guido Masera, Maurizio Martina, Guido Montorsi
VLSI Implementation of a Non-Binary Decoder Based on the Analog Digital Belief Propagation. IEEE Trans. Signal Process. 62 (15) (2014)
Carlo Condo, Maurizio Martina, Gianluca Piccinini, Guido Masera
Variable Parallelism Cyclic Redundancy Check Circuit for 3GPP-LTE/LTE-Advanced. IEEE Signal Process. Lett. 21 (11) (2014)
Maurizio Martina, Carlo Condo, Guido Masera, Maurizio Zamboni
A Joint Source/Channel Approach to Strengthen Embedded Programmable Devices against Flash Memory Errors. IEEE Embed. Syst. Lett. 6 (4) (2014)
Ali Zahir, Syed Azhar Ali Zaidi, Azzurra Pulimeno, Mariagrazia Graziano, Danilo Demarchi, Guido Masera, Gianluca Piccinini
Molecular transistor circuits: From device model to circuit simulation. NANOARCH (2014)
Bin Wu, Guido Masera
Analysis on parallel implementations of fixed-complexity sphere decoder. Sci. China Inf. Sci. 56 (4) (2013)
Carlo Condo, Amer Baghdadi, Guido Masera
A Joint Communication and Application Simulator for NoC-Based Custom SoCs: LDPC and Turbo Codes Parallel Decoding Case Study. DSD (2013)
Simone Zezza, Saeid Nooshabadi, Guido Masera
A 2.63 Mbit/s VLSI Implementation of SISO Arithmetic Decoders for High Performance Joint Source Channel Codes. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2013)
Ashfaq Ahmed, Muhammad Usman Shahid, Maurizio Martina, Enrico Magli, Guido Masera
VLSI Architecture for Low-Complexity Motion Estimation in H.264 Multiview Video Coding. DSD (2013)
Syed Azhar Ali Zaidi, Muhammad Awais, Carlo Condo, Maurizio Martina, Guido Masera
FPGA accelerator of Quasi cyclic EG-LDPC codes decoder for NAND flash memories. DASIP (2013)
Carlo Condo, Maurizio Martina, Guido Masera
VLSI Implementation of a Multi-Mode Turbo/LDPC Decoder Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2013)
Maurizio Martina, Guido Masera
Improving Network-on-Chip-based Turbo Decoder Architectures. J. Signal Process. Syst. 73 (1) (2013)
Andrea Bianco, Paolo Giaccone, Guido Masera, Marco Ricca
Power Control for Crossbar-Based Input-Queued Switches. IEEE Trans. Computers 62 (1) (2013)
Luca Gaetano Amarù, Maurizio Martina, Guido Masera
High Speed Architectures for Finding the First two Maximum/Minimum Values. IEEE Trans. Very Large Scale Integr. Syst. 20 (12) (2012)
Christina Gimmler-Dumont, Frank Kienle, Bin Wu, Guido Masera
A System View on Iterative MIMO Detection: Dynamic Sphere Detection versus Fixed Effort List Detection. VLSI Design 2012 (2012)
Bin Wu, Guido Masera
Efficient VLSI implementation of soft-input soft-output fixed-complexity sphere decoder. IET Commun. 6 (9) (2012)
Stylianos Papaharalabos, Panayiotis Takis Mathiopoulos, Guido Masera, Maurizio Martina
operator with reduced implementation complexity for turbo decoding. IET Commun. 6 (7) (2012)
Maurizio Martina, Guido Masera, Stylianos Papaharalabos, P. Takis Mathiopoulos, Fotios Gioulekas
Operator for Turbo and LDPC Decoders. IEEE Trans. Instrum. Meas. 61 (4) (2012)
Carlo Condo, Maurizio Martina, Guido Masera
A Network-on-Chip-based turbo/LDPC decoder architecture. DATE (2012)
Guido Masera, Amer Baghdadi, Frank Kienle, Christophe Moy
Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation. VLSI Design 2012 (2012)
M. Tamagnone, Maurizio Martina, Guido Masera
An application specific instruction set processor based implementation for signal detection in multiple antenna systems. Microprocess. Microsystems 36 (3) (2012)
Andrea Dario Giancarlo Biroli, Maurizio Martina, Guido Masera
An LDPC Decoder Architecture for Wireless Sensor Network Applications. Sensors 12 (2) (2012)

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Publication Activity (10 Years)

Top Topics

Top Venues

Guido Masera