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Improving Network-on-Chip-based Turbo Decoder Architectures.

Maurizio MartinaGuido Masera
Published in: J. Signal Process. Syst. (2013)
Keyphrases
  • network on chip
  • turbo codes
  • motion estimation
  • routing algorithm
  • response time
  • low complexity
  • error concealment
  • interconnection networks
  • network simulator