FPGA Accelerator of Algebraic Quasi Cyclic LDPC Codes for nand Flash Memories.
Syed Azhar Ali ZaidiAbuduwaili TuohetiMaurizio MartinaGuido MaseraPublished in: IEEE Des. Test (2016)
Keyphrases
- ldpc codes
- field programmable gate array
- low power consumption
- error correction
- embedded systems
- decoding algorithm
- message passing
- hardware implementation
- low cost
- low density parity check
- flash memory
- parallel computing
- rate allocation
- real time
- image transmission
- power consumption
- source coding
- low power
- associative memory
- higher order
- storage devices
- channel coding
- high speed
- frame rate
- end to end
- video coding
- image compression
- distributed systems
- bayesian networks