Maurizio Zamboni

Publication Activity (10 Years)

Years Active: 1987-2023
Publications (10 Years): 15

Top Topics

Electronic Circuits

Breast Cancer Detection

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

ACM J. Emerg. Technol. Comput. Syst.

IEEE Trans. Computers

Publications

Deborah Volpe, Giovanni Amedeo Cirillo, Maurizio Zamboni, Giovanna Turvani
Integration of Simulated Quantum Annealing in Parallel Tempering and Population Annealing for Heterogeneous-Profile QUBO Exploration. IEEE Access 11 (2023)
Mario Simoni, Giovanni Amedeo Cirillo, Giovanna Turvani, Mariagrazia Graziano, Maurizio Zamboni
Towards Compact Modeling of Noisy Quantum Computers: A Molecular-Spin-Qubit Case of Study. ACM J. Emerg. Technol. Comput. Syst. 18 (1) (2022)
Luigi Giuffrida, Deborah Volpe, Giovanni Amedeo Cirillo, Maurizio Zamboni, Giovanna Turvani
Engineering Grover Adaptive Search: Exploring the Degrees of Freedom for Efficient QUBO Solving. IEEE J. Emerg. Sel. Topics Circuits Syst. 12 (3) (2022)
Andrea Coluccio, Umberto Casale, Angela Guastamacchia, Giovanna Turvani, Marco Vacca, Massimo Ruo Roch, Maurizio Zamboni, Mariagrazia Graziano
Hybrid-SIMD: A Modular and Reconfigurable Approach to Beyond von Neumann Computing. IEEE Trans. Computers 71 (9) (2022)
Andrea Marchesin, Giovanna Turvani, Andrea Coluccio, Fabrizio Riente, Marco Vacca, Massimo Ruo Roch, Mariagrazia Graziano, Maurizio Zamboni
Octantis: An Exploration Tool for Beyond von Neumann architectures. DTIS (2021)
Milena Andrighetti, Giovanna Turvani, Giulia Santoro, Marco Vacca, Andrea Marchesin, Fabrizio Ottati, Massimo Ruo Roch, Mariagrazia Graziano, Maurizio Zamboni
Data Processing and Information Classification - An In-Memory Approach. Sensors 20 (6) (2020)
Milena Andrighetti, Giovanna Turvani, Giulia Santoro, Marco Vacca, Massimo Ruo Roch, Maurizio Graziano, Maurizio Zamboni
Bitmap Index: A Processing-in-Memory Reconfigurable Implementation. ApplePies (2019)
Simone Domenico Antonietta, Andrea Coluccio, Giovanna Turvani, Marco Vacca, Mariagrazia Graziano, Maurizio Zamboni
WINNER: a high speed high energy efficient Neural Network implementation for image classification. ICECS (2019)
Giulia Santoro, Marco Vacca, Matteo Bollo, Fabrizio Riente, Mariagrazia Graziano, Maurizio Zamboni
Exploration of multilayer field-coupled nanomagnetic circuits. Microelectron. J. 79 (2018)
Fabrizio Cairo, Marco Vacca, Giovanna Turvani, Maurizio Zamboni, Mariagrazia Graziano
Domain Wall Interconnections for NML. IEEE Trans. Very Large Scale Integr. Syst. 25 (11) (2017)
Giovanna Turvani, Fabrizio Riente, Fabrizio Cairo, Marco Vacca, Umberto Garlando, Maurizio Zamboni, Mariagrazia Graziano
Efficient and reliable fault analysis methodology for nanomagnetic circuits. Int. J. Circuit Theory Appl. 45 (5) (2017)
Fabrizio Riente, Giovanna Turvani, Marco Vacca, Massimo Ruo Roch, Maurizio Zamboni, Mariagrazia Graziano
ToPoliNano: A CAD Tool for Nano Magnetic Logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36 (7) (2017)
Matteo Bollo, Giulia Santoro, Umberto Garlando, Maurizio Zamboni
NANOcom: A Mosaic Approach for nanoelectronic circuits design. DTIS (2017)
Giovanni Causapruno, Fabrizio Riente, Giovanna Turvani, Marco Vacca, Massimo Ruo Roch, Maurizio Zamboni, Mariagrazia Graziano
Reconfigurable Systolic Array: From Architecture to Physical Design for NML. IEEE Trans. Very Large Scale Integr. Syst. 24 (11) (2016)
Giovanni Causapruno, Umberto Garlando, Fabrizio Cairo, Maurizio Zamboni, Mariagrazia Graziano
A Reconfigurable Array Architecture for NML. ISVLSI (2016)
Giovanni Causapruno, Gianvito Urgese, Marco Vacca, Mariagrazia Graziano, Maurizio Zamboni
Protein Alignment Systolic Array Throughput Optimization. IEEE Trans. Very Large Scale Integr. Syst. 23 (1) (2015)
Mario Cofano, Giulia Santoro, Marco Vacca, D. Pala, Giovanni Causapruno, Fabrizio Cairo, Fabrizio Riente, Giovanna Turvani, Massimo Ruo Roch, Mariagrazia Graziano, Maurizio Zamboni
Logic-in-Memory: A Nano Magnet Logic Implementation. ISVLSI (2015)
D. Pala, Giovanni Causapruno, Marco Vacca, Fabrizio Riente, Giovanna Turvani, Mariagrazia Graziano, Maurizio Zamboni
Logic-in-Memory architecture made real. ISCAS (2015)
Marco Vacca, Juanchi Wang, Mariagrazia Graziano, Massimo Ruo Roch, Maurizio Zamboni
Feedbacks in QCA: A Quantitative Approach. IEEE Trans. Very Large Scale Integr. Syst. 23 (10) (2015)
Giovanni Causapruno, Marco Vacca, Mariagrazia Graziano, Maurizio Zamboni
Interleaving in Systolic-Arrays: A Throughput Breakthrough. IEEE Trans. Computers 64 (7) (2015)
Davide Giri, Marco Vacca, Giovanni Causapruno, Wenjing Rao, Mariagrazia Graziano, Maurizio Zamboni
A standard cell approach for MagnetoElastic NML circuits. NANOARCH (2014)
Giovanna Turvani, A. Tohti, Matteo Bollo, Fabrizio Riente, Marco Vacca, Mariagrazia Graziano, Maurizio Zamboni
Physical design and testing of Nano Magnetic architectures. DTIS (2014)
Gianvito Urgese, Giulia Paciello, Andrea Acquaviva, Elisa Ficarra, Mariagrazia Graziano, Maurizio Zamboni
Dynamic Gap Selector: A Smith Waterman Sequence Alignment Algorithm with Affine Gap Model Optimization. IWBBIO (2014)
Xiaolu Guo, Mario R. Casu, Mariagrazia Graziano, Maurizio Zamboni
Simulation and design of an UWB imaging system for breast cancer detection. Integr. 47 (4) (2014)
Stefano Frache, Diego Chiabrando, Mariagrazia Graziano, Marco Vacca, Luca Boarino, Maurizio Zamboni
Enabling design and simulation of massive parallel nanoarchitectures. J. Parallel Distributed Comput. 74 (6) (2014)
Stefano Frache, Mariagrazia Graziano, Maurizio Zamboni
Nanoarray architectures multilevel simulation. ACM J. Emerg. Technol. Comput. Syst. 10 (1) (2014)
Mario R. Casu, Francesco Colonna, Marco Crepaldi, Danilo Demarchi, Mariagrazia Graziano, Maurizio Zamboni
UWB microwave imaging for breast cancer detection: Many-core, GPU, or FPGA? ACM Trans. Embed. Comput. Syst. 13 (3s) (2014)
Pasquale Ranone, Giovanna Turvani, Fabrizio Riente, Mariagrazia Graziano, Massimo Ruo Roch, Maurizio Zamboni
Fault tolerant nanoarray circuits: Automatic design and verification. VTS (2014)
Maurizio Martina, Carlo Condo, Guido Masera, Maurizio Zamboni
A Joint Source/Channel Approach to Strengthen Embedded Programmable Devices against Flash Memory Errors. IEEE Embed. Syst. Lett. 6 (4) (2014)
Manoj Kumar Yadav, Mario R. Casu, Maurizio Zamboni
LAURA-NoC: Local Automatic Rate Adjustment in Network-on-Chips With a Simple DVFS. IEEE Trans. Circuits Syst. II Express Briefs (10) (2013)
Xiaolu Guo, Mario R. Casu, Mariagrazia Graziano, Maurizio Zamboni
UWB receiver for breast cancer detection: Comparison between two different approaches. SoCC (2013)
Juanchi Wang, Marco Vacca, Mariagrazia Graziano, Massimo Ruo Roch, Maurizio Zamboni
Biosequences analysis on NanoMagnet Logic. ICICDT (2013)
Marco Vacca, Mariagrazia Graziano, Maurizio Zamboni
Nanomagnetic Logic Microprocessor: Hierarchical Power Model. IEEE Trans. Very Large Scale Integr. Syst. 21 (8) (2013)
Mariagrazia Graziano, Stefano Frache, Maurizio Zamboni
A Hardware Viewpoint on Biosequence Analysis: What's Next? ACM J. Emerg. Technol. Comput. Syst. 9 (4) (2013)
Xiaolu Guo, Mario R. Casu, Mariagrazia Graziano, Maurizio Zamboni
Breast cancer detection based on an UWB imaging system: Receiver design and simulations. ICICDT (2013)
Marco Vacca, Stefano Frache, Mariagrazia Graziano, L. Di Crescenzo, Fabrizio Cairo, Maurizio Zamboni
Automatic Place&Route of Nano-magnetic Logic circuits. NANOARCH (2013)
Francesco Colonna, Mariagrazia Graziano, Mario Roberto Casu, Xiaolu Guo, Maurizio Zamboni
Hardware Acceleration of Beamforming in a UWB Imaging Unit for Breast Cancer Detection. VLSI Design 2013 (2013)
D. Changdao, Mariagrazia Graziano, Ernesto Sánchez, Matteo Sonza Reorda, Maurizio Zamboni, N. Zhifan
On the functional test of the BTB logic in pipelined and superscalar processors. LATW (2013)
Stefano Frache, Diego Chiabrando, Mariagrazia Graziano, Fabrizio Riente, Giovanna Turvani, Maurizio Zamboni
ToPoliNano: nanoarchitectures design made real. NANOARCH (2012)
Manoj Kumar Yadav, Mario R. Casu, Maurizio Zamboni
DVFS Based on Voltage Dithering and Clock Scheduling for GALS Systems. ASYNC (2012)
Gianvito Urgese, Mariagrazia Graziano, Marco Vacca, Muhammad Awais, Stefano Frache, Maurizio Zamboni
Protein alignment HW/SW optimizations. ICECS (2012)
Stefano Frache, Luca Gaetano Amarù, Mariagrazia Graziano, Maurizio Zamboni
Nanofabric power analysis: Biosequence alignment case study. NANOARCH (2011)
Mario R. Casu, Massimo Ruo Roch, Sergio Tota, Maurizio Zamboni
A NoC-based hybrid message-passing/shared-memory approach to CMP design. Microprocess. Microsystems 35 (2) (2011)
Mariagrazia Graziano, Marco Vacca, Davide Blua, Maurizio Zamboni
Asynchrony in Quantum-Dot Cellular Automata Nanocomputation: Elixir or Poison? IEEE Des. Test Comput. 28 (5) (2011)
Marco Vacca, Mariagrazia Graziano, Maurizio Zamboni
Asynchronous Solutions for Nanomagnetic Logic Circuits. ACM J. Emerg. Technol. Comput. Syst. 7 (4) (2011)
Sergio Tota, Mario R. Casu, Massimo Ruo Roch, Luca Rostagno, Maurizio Zamboni
MEDEA: a hybrid shared-memory/message-passing multiprocessor NoC-based architecture. DATE (2010)
Stefano Frache, Mariagrazia Graziano, Maurizio Zamboni
A flexible simulation methodology and tool for nanoarray-based architectures. ICCD (2010)
Mario R. Casu, Mariagrazia Graziano, Maurizio Zamboni
A Fully Differential Digital CMOS UWB Pulse Generator. Circuits Syst. Signal Process. 28 (5) (2009)
Marco Crepaldi, Mario R. Casu, Mariagrazia Graziano, Maurizio Zamboni
A mixed-signal demodulator for a low-complexity IR-UWB receiver: Methodology, simulation and design. Integr. 42 (1) (2009)
Sergio Tota, Mario R. Casu, Massimo Ruo Roch, Luca Macchiarulo, Maurizio Zamboni
A Case Study for NoC-Based Homogeneous MPSoC Architectures. IEEE Trans. Very Large Scale Integr. Syst. 17 (3) (2009)
Marco Crepaldi, Mario R. Casu, Mariagrazia Graziano, Maurizio Zamboni
An effective AMS top-down methodology applied to the design of a mixed-signal UWB system-on-chip. DATE (2007)
Sergio Tota, Mario R. Casu, Paolo Motto Ros, Massimo Ruo Roch, Maurizio Zamboni
The NoCRay Graphic Accelerator: a Case-study for MP-SoC Network-on-Chip Design Methodology. SoC (2007)
Sergio Tota, Mario R. Casu, Paolo Motto Ros, Massimo Ruo Roch, Maurizio Zamboni
A methodology and a case-study for network-on-chip based MP-SoC architectures. Nano-Net (2007)
Mariagrazia Graziano, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
Effects of temperature in deep-submicron global interconnect optimization in future technology nodes. Microelectron. J. 35 (10) (2004)
Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
An electromigration and thermal model of power wires for a priori high-level reliability prediction. IEEE Trans. Very Large Scale Integr. Syst. 12 (4) (2004)
Federico Quaglio, Maurizio Martina, Fabrizio Vacca, Guido Masera, Andrea Molino, Gianluca Piccinini, Maurizio Zamboni
Wireless sensor networks: a power-scalable motion estimation IP for hybrid video coding. FPGA (2003)
M. Addino, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization. PATMOS (2003)
Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
Coupled electro-thermal modeling and optimization of clock networks. Microelectron. J. 34 (12) (2003)
Maurizio Martina, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
Novel JPEG 2000 Compliant DWT and IWT VLSI Implementations. J. VLSI Signal Process. 35 (2) (2003)
Mario R. Casu, Mariagrazia Graziano, Gianluca Piccinini, Guido Masera, Maurizio Zamboni
Effects of Temperature in Deep-Submicron Global Interconnect Optimization. PATMOS (2003)
Guido Masera, Marco Mazza, Gianluca Piccinini, Fabrizio Viglione, Maurizio Zamboni
Architectural strategies for low-power VLSI turbo decoders. IEEE Trans. Very Large Scale Integr. Syst. 10 (3) (2002)
Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, M. M. Prono, Maurizio Zamboni
Clock Distribution Network Optimization under Self-Heating and Timing Constraints. PATMOS (2002)
Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni
Reconfigurable DSP IP for multimedia applications. ICASSP (2002)
Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni
System architecture for error-resilient, embedded JPEG2000 wireless delivery. DSP (2002)
Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni
Embedded IWT evaluation in reconfigurable wireless sensor network. ICECS (2002)
Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni
Energy Evaluation on a Reconfigurable, Multimedia-Oriented Wireless Sensor. FPL (2002)
Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
Hierarchical power supply noise evaluation for early power grid design prediction. SLIP (2001)
Mario R. Casu, Gianluca Piccinini, Guido Masera, Maurizio Zamboni
Synthesis of low-leakage PD-SOI circuits with body-biasing. ISLPED (2001)
Marco Delaurenti, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
Switching Noise Analysis Framework For High Speed Logic Families. VLSI Design (2001)
Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni
JPEG 2000: finite precision representation and hardware implications. ICECS (2001)
Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni
Reconfigurable coprocessor based JPEG 2000 implementation. ICECS (2001)
Mariagrazia Graziano, Marco Delaurenti, Maurizio Zamboni
Power supply design parameters prediction for high performance IC design flows. SLIP (2000)
Mario Roberto Casu, Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni
A high accuracy-low complexity model for CMOS delays. ISCAS (2000)
Mariagrazia Graziano, Marco Delaurenti, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
Noise Safety Design Methodologies. ISQED (2000)
Fabrizio Viglione, Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni
A 50 Mbit/s Iterative Turbo-Decoder. DATE (2000)
Marco Delaurenti, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
A global optimization tool for CMOS logic circuits. ICECS (1999)
Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni
VLSI architectures for turbo codes. IEEE Trans. Very Large Scale Integr. Syst. 7 (3) (1999)
Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni
New 2 Gbit/s CMOS I/O pads. Great Lakes Symposium on VLSI (1999)
Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni
A Quantitative Approach to the Design of an Optimized Hardware Interpreter for Java Byte-Code. Applied Informatics (1999)
Pasquale Cocchini, Massoud Pedram, Gianluca Piccinini, Maurizio Zamboni
Fanout optimization under a submicron transistor-level delay model. ICCAD (1998)
A. Brizio, Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni
A 500 MHz 2d-DWT VLSI processor. EUSIPCO (1998)
Pierre Combelles, Christophe Del Toso, Dietmar Hepper, David Le Goff, J. J. Ma, Patrick Robertson, Fabio Scalise, Laurent Soyer, Maurizio Zamboni
A receiver architecture conforming to the OFDM based digital video broadcasting standard for terrestrial transmission (DVB-T). ICC (1998)
Pasquale Cocchini, Gianluca Piccinini, Maurizio Zamboni
A comprehensive submicrometer MOST delay model and its application to CMOS buffers. IEEE J. Solid State Circuits 32 (8) (1997)
F. Fraternali, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
A 650 MHz pipelined MAC for DSP applications using a new clocking strategy. EUSIPCO (1996)
Pierre Plaza, Juan Carlos Diaz, Fermín Calvo, Luis A. Merayo, Maurizio Zamboni, Pietro Scarfone, Marco Barbini
Input and output processor for an ATM high speed switch (2.5 Gb/s): the CMC. ED&TC (1995)
Guido Albertengo, Pierluigi Civera, Renato Lo Cigno, Gianluca Piccinini, Maurizio Zamboni, Flaminio Borgonovo, Luigi Fratta, Giuseppe Panizzardi
Deflection network: Principles, implementation, services. Eur. Trans. Telecommun. 3 (2) (1992)
Pierluigi Civera, Gianluca Piccinini, Maurizio Zamboni
Implementation studies for a VLSI Prolog coprocessor. IEEE Micro 9 (1) (1989)
Pierluigi Civera, F. Maddaleno, Gianluca Piccinini, Maurizio Zamboni
An Experimental VLSI Prolog Interpreter: Preliminary Measurements and Results. ISCA (1987)
Pierluigi Civera, Gianluca Piccinini, Maurizio Zamboni
Design considerations on a VLSI Prolog interpreter. Microprocess. Microprogramming 21 (1-5) (1987)