Gianluca Piccinini

Publication Activity (10 Years)

Years Active: 1987-2023
Publications (10 Years): 10

Top Topics

Probability Ranking Principle

Latest Developments

Molecular Structures

Top Venues

ACM J. Emerg. Technol. Comput. Syst.

IEEE Signal Process. Lett.

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Yuri Ardesi, Umberto Garlando, Fabrizio Riente, Giuliana Beretta, Gianluca Piccinini, Mariagrazia Graziano
Taming Molecular Field-Coupling for Nanocomputing Design. ACM J. Emerg. Technol. Comput. Syst. 19 (1) (2023)
Fabrizio Mo, Chiara Elfi Spano, Yuri Ardesi, Massimo Ruo Roch, Gianluca Piccinini, Mariagrazia Graziano
Design of Pyrrole-Based Gate-Controlled Molecular Junctions Optimized for Single-Molecule Aflatoxin B1 Detection. Sensors 23 (3) (2023)
Davide Costa, Mario Simoni, Gianluca Piccinini, Mariagrazia Graziano
Advances in Modeling of Noisy Quantum Computers: Spin Qubits in Semiconductor Quantum Dots. IEEE Access 11 (2023)
Yuri Ardesi, Giuliana Beretta, Christian Fabiano, Mariagrazia Graziano, Gianluca Piccinini
A Reconfigurable Field-Coupled Nanocomputing Paradigm on Uniform Molecular Monolayers. ICRC (2021)
Yuri Ardesi, Giovanna Turvani, Mariagrazia Graziano, Gianluca Piccinini
SCERPA Simulation of Clocked Molecular Field-Coupling Nanocomputing. IEEE Trans. Very Large Scale Integr. Syst. 29 (3) (2021)
Yuri Ardesi, Ruiyu Wang, Giovanna Turvani, Gianluca Piccinini, Mariagrazia Graziano
SCERPA: A Self-Consistent Algorithm for the Evaluation of the Information Propagation in Molecular Field-Coupled Nanocomputing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (10) (2020)
Yuri Ardesi, Luca Gnoli, Mariagrazia Graziano, Gianluca Piccinini
Bistable Propagation of Monostable Molecules in Molecular Field-Coupled Nanocomputing. PRIME (2019)
Malik Ashter Mehdy, Aleandro Antidormi, Mariagrazia Graziano, Gianluca Piccinini
Nanoarrays for Systolic Biosequence Analysis. J. Circuits Syst. Comput. 27 (12) (2018)
Mariagrazia Graziano, Azzurra Pulimeno, Ruiyu Wang, Xiang Wei, Massimo Ruo Roch, Gianluca Piccinini
Process Variability and Electrostatic Analysis of Molecular QCA. ACM J. Emerg. Technol. Comput. Syst. 12 (2) (2015)
Maurizio Martina, Guido Masera, Massimo Ruo Roch, Gianluca Piccinini
Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2015)
Guoping Xiao, Maurizio Martina, Guido Masera, Gianluca Piccinini
A Parallel Radix-Sort-Based VLSI Architecture for Finding the First W Maximum/Minimum Values. IEEE Trans. Circuits Syst. II Express Briefs (11) (2014)
Carlo Condo, Maurizio Martina, Gianluca Piccinini, Guido Masera
Variable Parallelism Cyclic Redundancy Check Circuit for 3GPP-LTE/LTE-Advanced. IEEE Signal Process. Lett. 21 (11) (2014)
Ali Zahir, Syed Azhar Ali Zaidi, Azzurra Pulimeno, Mariagrazia Graziano, Danilo Demarchi, Guido Masera, Gianluca Piccinini
Molecular transistor circuits: From device model to circuit simulation. NANOARCH (2014)
Azzurra Pulimeno, Mariagrazia Graziano, Ruiyu Wang, Danilo Demarchi, Gianluca Piccinini
Charge distribution in a molecular QCA wire based on bis-ferrocene molecules. NANOARCH (2013)
Ismael Rattalino, Paolo Motto Ros, Irene Taurino, Fernando Cortes-Salazar, Gianluca Piccinini, Danilo Demarchi, Giovanni De Micheli, Sandro Carrara
Nanogap-based enzymatic-free electrochemical detection of glucose. BioCAS (2013)
Azzurra Pulimeno, Mariagrazia Graziano, Gianluca Piccinini
UDSM Trends Comparison: From Technology Roadmap to UltraSparc Niagara2. IEEE Trans. Very Large Scale Integr. Syst. 20 (7) (2012)
Maurizio Martina, Guido Masera, Gianluca Piccinini
Scalable low-complexity B-spline discrete wavelet transform architecture. IET Circuits Devices Syst. 4 (2) (2010)
Mariagrazia Graziano, Gianluca Piccinini
Statistical power supply dynamic noise prediction in hierarchical power grid and package networks. Integr. 41 (4) (2008)
Mariagrazia Graziano, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
Effects of temperature in deep-submicron global interconnect optimization in future technology nodes. Microelectron. J. 35 (10) (2004)
Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
An electromigration and thermal model of power wires for a priori high-level reliability prediction. IEEE Trans. Very Large Scale Integr. Syst. 12 (4) (2004)
Federico Quaglio, Maurizio Martina, Fabrizio Vacca, Guido Masera, Andrea Molino, Gianluca Piccinini, Maurizio Zamboni
Wireless sensor networks: a power-scalable motion estimation IP for hybrid video coding. FPGA (2003)
M. Addino, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization. PATMOS (2003)
Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
Coupled electro-thermal modeling and optimization of clock networks. Microelectron. J. 34 (12) (2003)
Maurizio Martina, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
Novel JPEG 2000 Compliant DWT and IWT VLSI Implementations. J. VLSI Signal Process. 35 (2) (2003)
Mario R. Casu, Mariagrazia Graziano, Gianluca Piccinini, Guido Masera, Maurizio Zamboni
Effects of Temperature in Deep-Submicron Global Interconnect Optimization. PATMOS (2003)
Guido Masera, Marco Mazza, Gianluca Piccinini, Fabrizio Viglione, Maurizio Zamboni
Architectural strategies for low-power VLSI turbo decoders. IEEE Trans. Very Large Scale Integr. Syst. 10 (3) (2002)
Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, M. M. Prono, Maurizio Zamboni
Clock Distribution Network Optimization under Self-Heating and Timing Constraints. PATMOS (2002)
Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni
Reconfigurable DSP IP for multimedia applications. ICASSP (2002)
Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni
System architecture for error-resilient, embedded JPEG2000 wireless delivery. DSP (2002)
Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni
Embedded IWT evaluation in reconfigurable wireless sensor network. ICECS (2002)
Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni
Energy Evaluation on a Reconfigurable, Multimedia-Oriented Wireless Sensor. FPL (2002)
Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
Hierarchical power supply noise evaluation for early power grid design prediction. SLIP (2001)
Mario R. Casu, Gianluca Piccinini, Guido Masera, Maurizio Zamboni
Synthesis of low-leakage PD-SOI circuits with body-biasing. ISLPED (2001)
Marco Delaurenti, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
Switching Noise Analysis Framework For High Speed Logic Families. VLSI Design (2001)
Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni
JPEG 2000: finite precision representation and hardware implications. ICECS (2001)
Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni
Reconfigurable coprocessor based JPEG 2000 implementation. ICECS (2001)
Mario Roberto Casu, Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni
A high accuracy-low complexity model for CMOS delays. ISCAS (2000)
Mariagrazia Graziano, Marco Delaurenti, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
Noise Safety Design Methodologies. ISQED (2000)
Fabrizio Viglione, Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni
A 50 Mbit/s Iterative Turbo-Decoder. DATE (2000)
Marco Delaurenti, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
A global optimization tool for CMOS logic circuits. ICECS (1999)
Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni
VLSI architectures for turbo codes. IEEE Trans. Very Large Scale Integr. Syst. 7 (3) (1999)
Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni
New 2 Gbit/s CMOS I/O pads. Great Lakes Symposium on VLSI (1999)
Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni
A Quantitative Approach to the Design of an Optimized Hardware Interpreter for Java Byte-Code. Applied Informatics (1999)
Pasquale Cocchini, Massoud Pedram, Gianluca Piccinini, Maurizio Zamboni
Fanout optimization under a submicron transistor-level delay model. ICCAD (1998)
A. Brizio, Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni
A 500 MHz 2d-DWT VLSI processor. EUSIPCO (1998)
Pasquale Cocchini, Gianluca Piccinini, Maurizio Zamboni
A comprehensive submicrometer MOST delay model and its application to CMOS buffers. IEEE J. Solid State Circuits 32 (8) (1997)
F. Fraternali, Guido Masera, Gianluca Piccinini, Maurizio Zamboni
A 650 MHz pipelined MAC for DSP applications using a new clocking strategy. EUSIPCO (1996)
Guido Albertengo, Pierluigi Civera, Renato Lo Cigno, Gianluca Piccinini, Maurizio Zamboni, Flaminio Borgonovo, Luigi Fratta, Giuseppe Panizzardi
Deflection network: Principles, implementation, services. Eur. Trans. Telecommun. 3 (2) (1992)
Pierluigi Civera, Gianluca Piccinini, Maurizio Zamboni
Implementation studies for a VLSI Prolog coprocessor. IEEE Micro 9 (1) (1989)
Pierluigi Civera, F. Maddaleno, Gianluca Piccinini, Maurizio Zamboni
An Experimental VLSI Prolog Interpreter: Preliminary Measurements and Results. ISCA (1987)
Pierluigi Civera, Gianluca Piccinini, Maurizio Zamboni
Design considerations on a VLSI Prolog interpreter. Microprocess. Microprogramming 21 (1-5) (1987)