A 500 MHz 2d-DWT VLSI processor.

A. Brizio Guido Masera Gianluca Piccinini Massimo Ruo Roch Maurizio Zamboni

Published in: EUSIPCO (1998)

Keyphrases

high speed
single chip
low power
gate array
memory subsystem
vlsi design
signal processing
fpga device
low cost
xilinx virtex
real time
hardware architecture
vlsi circuits
chip design
wavelet transformation
computer architecture
parallel algorithm
image processing