Pasquale Cocchini

Publication Activity (10 Years)

Years Active: 1997-2023
Publications (10 Years): 6

Top Topics

Multilayer Perceptron

Hardware Design

Top Venues

IACR Cryptol. ePrint Arch.

Publications

Zhenkun Yang, Wen Wang, Jeremy Casas, Pasquale Cocchini, Jin Yang
Towards A Correct-by-Construction FHE Model. IACR Cryptol. ePrint Arch. 2023 (2023)
Yanzhao Wang, Fei Xie, Zhenkun Yang, Jeremy Casas, Pasquale Cocchini, Jin Yang
An Automated Verification Framework for HalideIR-Based Compiler Transformations. DATE (2023)
Yanzhao Wang, Fei Xie, Zhenkun Yang, Pasquale Cocchini, Jin Yang
An Equivalence Checking Framework for Agile Hardware Design. ASP-DAC (2023)
Debjit Pal, Yi-Hsiang Lai, Shaojie Xiang, Niansong Zhang, Hongzheng Chen, Jeremy Casas, Pasquale Cocchini, Zhenkun Yang, Jin Yang, Louis-Noël Pouchet, Zhiru Zhang
Accelerator design with decoupled hardware customizations: benefits and challenges: invited. DAC (2022)
Suvadeep Banerjee, Steve Burns, Pasquale Cocchini, Abhijit Davare, Shweta Jain, Desmond Kirkpatrick, Anton Sorokin, Jin Yang, Zhenkun Yang
A Highly Configurable Hardware/Software Stack for DNN Inference Acceleration. CoRR (2021)
Yash Akhauri, Adithya Niranjan, J. Pablo Muñoz, Suvadeep Banerjee, Abhijit Davare, Pasquale Cocchini, Anton A. Sorokin, Ravi Iyer, Nilesh Jain
RHNAS: Realizable Hardware and Neural Architecture Search. CoRR (2021)
Prashant Saxena, Noel Menezes, Pasquale Cocchini, Desmond Kirkpatrick
Repeater scaling and its impact on CAD. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (4) (2004)
Prashant Saxena, Noel Menezes, Pasquale Cocchini, Desmond Kirkpatrick
The scaling challenge: can correct-by-construction design help? ISPD (2003)
Pasquale Cocchini
A methodology for optimal repeater insertion in pipelined interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (12) (2003)
Pasquale Cocchini
Concurrent flip-flop and repeater insertion for high performance integrated circuits. ICCAD (2002)
Pasquale Cocchini, Massoud Pedram
Fanout optimization using bipolar LT-trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (3) (2000)
Pasquale Cocchini, Massoud Pedram, Gianluca Piccinini, Maurizio Zamboni
Fanout optimization under a submicron transistor-level delay model. ICCAD (1998)
Pasquale Cocchini, Gianluca Piccinini, Maurizio Zamboni
A comprehensive submicrometer MOST delay model and its application to CMOS buffers. IEEE J. Solid State Circuits 32 (8) (1997)