Yi-Hsiang Lai

Publication Activity (10 Years)

Years Active: 2014-2024
Publications (10 Years): 10

Top Topics

Benchmark Suite

Delay Insensitive

Top Venues

Publications

Ruixin Wang, Minghai Lu, Cody Hao Yu, Yi-Hsiang Lai, Tianyi Zhang
Automated Deep Learning Optimization via DSL-Based Source Code Transformation. CoRR (2024)
Shaojie Xiang, Yi-Hsiang Lai, Yuan Zhou, Hongzheng Chen, Niansong Zhang, Debjit Pal, Zhiru Zhang
HeteroFlow: An Accelerator Programming Model with Decoupled Data Placement for Software-Defined FPGAs. FPGA (2022)
Debjit Pal, Yi-Hsiang Lai, Shaojie Xiang, Niansong Zhang, Hongzheng Chen, Jeremy Casas, Pasquale Cocchini, Zhenkun Yang, Jin Yang, Louis-Noël Pouchet, Zhiru Zhang
Accelerator design with decoupled hardware customizations: benefits and challenges: invited. DAC (2022)
Zhi Chen, Cody Hao Yu, Trevor Morris, Jorn Tuyls, Yi-Hsiang Lai, Jared Roesch, Elliott Delaye, Vin Sharma, Yida Wang
Bring Your Own Codegen to Deep Learning Compiler. CoRR (2021)
Yi-Hsiang Lai, Ecenur Ustun, Shaojie Xiang, Zhenman Fang, Hongbo Rong, Zhiru Zhang
Programming and Synthesis for Software-defined FPGA Acceleration: Status and Future Prospects. ACM Trans. Reconfigurable Technol. Syst. 14 (4) (2021)
Yi-Hsiang Lai, Hongbo Rong, Size Zheng, Weihao Zhang, Xiuping Cui, Yunshan Jia, Jie Wang, Brendan Sullivan, Zhiru Zhang, Yun Liang, Youhui Zhang, Jason Cong, Nithin George, Jose Alvarez, Christopher J. Hughes, Pradeep Dubey
SuSy: A Programming Model for Productive Construction of High-Performance Systolic Arrays on FPGAs. ICCAD (2020)
Yi-Hsiang Lai, Yuze Chi, Yuwei Hu, Jie Wang, Cody Hao Yu, Yuan Zhou, Jason Cong, Zhiru Zhang
HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing. FPGA (2019)
Yuan Zhou, Udit Gupta, Steve Dai, Ritchie Zhao, Nitish Kumar Srivastava, Hanchen Jin, Joseph Featherston, Yi-Hsiang Lai, Gai Liu, Gustavo Angarita Velasquez, Wenping Wang, Zhiru Zhang
Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAs. FPGA (2018)
Yi-Hsiang Lai, Chi-Chuan Chuang, Jie-Hong R. Jiang
Scalable Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (11) (2016)
Nian-Ze Lee, Hao-Yuan Kuo, Yi-Hsiang Lai, Jie-Hong R. Jiang
Analytic approaches to the collapse operation and equivalence verification of threshold logic circuits. ICCAD (2016)
Yi-Hsiang Lai, Chi-Chuan Chuang, Jie-Hong R. Jiang
A General Framework for Efficient Performance Analysis of Acyclic Asynchronous Pipelines. ICCAD (2015)
Chun-Hong Shih, Yi-Hsiang Lai, Jie-Hong Roland Jiang
SPOCK: Static Performance Analysis and Deadlock Verification for Efficient Asynchronous Circuit Synthesis. ICCAD (2015)
Bo-Yuan Huang, Yi-Hsiang Lai, Jie-Hong Roland Jiang
Asynchronous QDI Circuit Synthesis from Signal Transition Protocols. ICCAD (2015)
Chi-Chuan Chuang, Yi-Hsiang Lai, Jie-Hong R. Jiang
Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits. DAC (2014)