Jie Wang

Publication Activity (10 Years)

Years Active: 2015-2023
Publications (10 Years): 28

Top Topics

Parallel Architecture

Physical Design

Matrix Multiplication

Top Venues

ACM Trans. Reconfigurable Technol. Syst.

Publications

Yuze Chi, Weikang Qiao, Atefeh Sohrabizadeh, Jie Wang, Jason Cong
Democratizing Domain-Specific Computing. Commun. ACM 66 (1) (2023)
Suhail Basalama, Jie Wang, Jason Cong
A Comprehensive Automated Exploration Framework for Systolic Array Designs. DAC (2023)
Suhail Basalama, Atefeh Sohrabizadeh, Jie Wang, Licheng Guo, Jason Cong
FlexCNN: An End-to-end Framework for Composing CNN Accelerators on FPGA. ACM Trans. Reconfigurable Technol. Syst. 16 (2) (2023)
Licheng Guo, Yuze Chi, Jason Lau, Linghao Song, Xingyu Tian, Moazin Khatti, Weikang Qiao, Jie Wang, Ecenur Ustun, Zhenman Fang, Zhiru Zhang, Jason Cong
TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical Design. ACM Trans. Reconfigurable Technol. Syst. 16 (4) (2023)
Licheng Guo, Pongstorn Maidee, Yun Zhou, Chris Lavin, Jie Wang, Yuze Chi, Weikang Qiao, Alireza Kaviani, Zhiru Zhang, Jason Cong
RapidStream: Parallel Physical Implementation of FPGA HLS Designs. FPGA (2022)
Licheng Guo, Yuze Chi, Jason Lau, Linghao Song, Xingyu Tian, Moazin Khatti, Weikang Qiao, Jie Wang, Ecenur Ustun, Zhenman Fang, Zhiru Zhang, Jason Cong
TAPA: A Scalable Task-Parallel Dataflow Programming Framework for Modern FPGAs with Co-Optimization of HLS and Physical Design. CoRR (2022)
Yuze Chi, Weikang Qiao, Atefeh Sohrabizadeh, Jie Wang, Jason Cong
Democratizing Domain-Specific Computing. CoRR (2022)
Suhail Basalama, Atefeh Sohrabizadeh, Jie Wang, Jason Cong
A Versatile Systolic Array for Transposed and Dilated Convolution on FPGA. FCCM (2022)
Yuze Chi, Licheng Guo, Jason Lau, Young-kyu Choi, Jie Wang, Jason Cong
Extending High-Level Synthesis for Task-Parallel Programs. FCCM (2021)
Yuze Chi, Licheng Guo, Young-kyu Choi, Jie Wang, Jason Cong
Extending High-Level Synthesis for Task-Parallel Programs. FPGA (2021)
Licheng Guo, Yuze Chi, Jie Wang, Jason Lau, Weikang Qiao, Ecenur Ustun, Zhiru Zhang, Jason Cong
AutoBridge: Coupling Coarse-Grained Floorplanning and Pipelining for High-Frequency HLS Design on Multi-Die FPGAs. FPGA (2021)
Jie Wang, Licheng Guo, Jason Cong
AutoSA: A Polyhedral Compiler for High-Performance Systolic Arrays on FPGA. FPGA (2021)
Peipei Zhou, Jiayi Sheng, Cody Hao Yu, Peng Wei, Jie Wang, Di Wu, Jason Cong
MOCHA: Multinode Cost Optimization in Heterogeneous Clouds with Accelerators. FPGA (2021)
Jie Wang, Jason Cong
Search for Optimal Systolic Arrays: A Comprehensive Automated Exploration Framework and Lessons Learned. CoRR (2021)
Licheng Guo, Jason Lau, Yuze Chi, Jie Wang, Cody Hao Yu, Zhe Chen, Zhiru Zhang, Jason Cong
Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency. DAC (2020)
Atefeh Sohrabizadeh, Jie Wang, Jason Cong
End-to-End Optimization of Deep Learning Applications. FPGA (2020)
Licheng Guo, Jason Lau, Yuze Chi, Jie Wang, Cody Hao Yu, Zhe Chen, Zhiru Zhang, Jason Cong
Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency. FPGA (2020)
Young-kyu Choi, Yuze Chi, Jie Wang, Licheng Guo, Jason Cong
When HLS Meets FPGA HBM: Benchmarking and Bandwidth Optimization. CoRR (2020)
Yuze Chi, Licheng Guo, Young-kyu Choi, Jie Wang, Jason Cong
Extending High-Level Synthesis for Task-Parallel Programs. CoRR (2020)
Michael Lo, Zhenman Fang, Jie Wang, Peipei Zhou, Mau-Chung Frank Chang, Jason Cong
Algorithm-Hardware Co-design for BQSR Acceleration in Genome Analysis ToolKit. FCCM (2020)
Young-kyu Choi, Yuze Chi, Jie Wang, Jason Cong
FLASH: Fast, Parallel, and Accurate Simulator for HLS. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (12) (2020)
Yi-Hsiang Lai, Yuze Chi, Yuwei Hu, Jie Wang, Cody Hao Yu, Yuan Zhou, Jason Cong, Zhiru Zhang
HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing. FPGA (2019)
Yuze Chi, Young-kyu Choi, Jason Cong, Jie Wang
Rapid Cycle-Accurate Simulator for High-Level Synthesis. FPGA (2019)
Jason Cong, Jie Wang
Automatic Interior I/O Elimination in Systolic Array Architecture. FCCM (2018)
Jason Cong, Jie Wang
PolySA: polyhedral-based systolic array auto-compilation. ICCAD (2018)
Yuze Chi, Young-kyu Choi, Jason Cong, Jie Wang
Rapid Cycle-Accurate Simulator for High-Level Synthesis. CoRR (2018)
Jie Wang, Xinfeng Xie, Jason Cong
Communication Optimization on GPU: A Case Study of Sequence Alignment Algorithms. IPDPS (2017)
Jiantao Qiu, Jie Wang, Song Yao, Kaiyuan Guo, Boxun Li, Erjin Zhou, Jincheng Yu, Tianqi Tang, Ningyi Xu, Sen Song, Yu Wang, Huazhong Yang
Going Deeper with Embedded FPGA Platform for Convolutional Neural Network. FPGA (2016)
Jie Wang, Jason Cong
Customizable and High Performance Matrix Multiplication Kernel on FPGA (Abstract Only). FPGA (2015)