Prashant Saxena

Publication Activity (10 Years)

Years Active: 1994-2022
Publications (10 Years): 7

Top Topics

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Zhaowei Liu, Andrew McBride, Abhishek Ghosh, Luca Heltai, Weicheng Huang, Tiantang Yu, Paul Steinmann, Prashant Saxena
Computational bifurcation analysis of hyperelastic thin shells. CoRR (2022)
T. Patrick Xiao, Ben Feinberg, Christopher H. Bennett, Vineet Agrawal, Prashant Saxena, Venkatraman Prabhakar, Krishnaswamy Ramkumar, Harsha Medu, Vijay Raghavan, Ramesh Chettuvetty, Sapan Agarwal, Matthew J. Marinella
An Accurate, Error-Tolerant, and Energy-Efficient Neural Network Inference Engine Based on SONOS Analog Memory. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (4) (2022)
Zhaowei Liu, Andrew McBride, Prashant Saxena, Luca Heltai, Yilin Qu, Paul Steinmann
Vibration Analysis of Piezoelectric Kirchhoff-Love Shells based on Catmull-Clark Subdivision Surfaces. CoRR (2021)
Bhumika Shah, Ankita Sinha, Prashant Saxena
Image GPT with Super Resolution. FICTA (1) (2021)
T. Patrick Xiao, Ben Feinberg, Christopher H. Bennett, Venkatraman Prabhakar, Prashant Saxena, Vineet Agrawal, Sapan Agarwal, Matthew J. Marinella
On the Accuracy of Analog Neural Network Inference Accelerators. CoRR (2021)
Zhaowei Liu, Andrew McBride, Prashant Saxena, Paul Steinmann
Aspects of Isogeometric Analysis with Catmull-Clark Subdivision Surfaces. CoRR (2019)
Wei-Ting Jonas Chan, Pei-Hsin Ho, Andrew B. Kahng, Prashant Saxena
Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine Learning. ISPD (2017)
Haris Volos, Sanketh Nalli, Sankaralingam Panneerselvam, Venkatanathan Varadarajan, Prashant Saxena, Michael M. Swift
Aerie: flexible file-system interfaces to storage-class memory. EuroSys (2014)
Tong Gao, Prashant Saxena
On pioneering nanometer-era routing problems. ISPD (2012)
Prashant Saxena, Yao-Wen Chang
Guest Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (2) (2011)
Stephen M. Plaza, Prashant Saxena, Thomas R. Shiple, Pei-Hsin Ho
Multi-mode redundancy removal. ISQED (2011)
Gi-Joon Nam, Prashant Saxena
Guest Editorial. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (2) (2010)
Prashant Saxena, Vishal Khandelwal, Changge Qiao, Pei-Hsin Ho, J.-C. Lin, Mahesh A. Iyer
On improving optimization effectiveness in interconnect-driven physical synthesis. ISPD (2009)
Prashant Saxena
On controlling perturbation due to repeaters during quadratic placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (9) (2006)
Prashant Saxena
The scaling of interconnect buffer needs. SLIP (2006)
Rupesh S. Shelar, Prashant Saxena, Sachin S. Sapatnekar
Technology Mapping Algorithm Targeting Routing Congestion Under Delay Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (4) (2006)
Brent Goplen, Prashant Saxena, Sachin S. Sapatnekar
Net weighting to reduce repeater counts during placement. DAC (2005)
Rupesh S. Shelar, Prashant Saxena, Xinning Wang, Sachin S. Sapatnekar
An efficient technology mapping algorithm targeting routing congestion under delay constraints. ISPD (2005)
Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannal Yang, Prashant Saxena, Vijay Pitchumani
A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation. ISCAS (6) (2005)
Prashant Saxena, Kumar N. Lalgudi, Hans J. Greub, Janet Meiling Wang Roveda
A perturbation-aware noise convergence methodology for high frequency microprocessors. ASP-DAC (2005)
Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang
A predictive distributed congestion metric with application to technology mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (5) (2005)
Prashant Saxena, Bill Halpin
Modeling repeaters explicitly within analytical placement. DAC (2004)
Prashant Saxena, Noel Menezes, Pasquale Cocchini, Desmond Kirkpatrick
Repeater scaling and its impact on CAD. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (4) (2004)
Janet Meiling Wang, Prashant Saxena, Omar Hafiz, Xing Wang
Realizable parasitic reduction for distributed interconnects using matrix pencil technique. ASP-DAC (2004)
Desmond Kirkpatrick, Peter J. Osler, Louis Scheffer, Prashant Saxena, Dennis Sylvester
The great interconnect buffering debate: are you a chicken or an ostrich? ISPD (2004)
Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang
A predictive distributed congestion metric and its application to technology mapping. ISPD (2004)
Prashant Saxena, Satyanarayan Gupta
On integrating power and signal routing for shield count minimization in congested regions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (4) (2003)
Prashant Saxena, Noel Menezes, Pasquale Cocchini, Desmond Kirkpatrick
The scaling challenge: can correct-by-construction design help? ISPD (2003)
Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Prashant Saxena, C. L. Liu, S.-M. S. Kang
Coupling delay optimization by temporal decorrelation using dual threshold voltage technique. IEEE Trans. Very Large Scale Integr. Syst. 11 (5) (2003)
B. Chappell, Xinning Wang, Priyadarsan Patra, Prashant Saxena, J. Vendrell, Satyanarayan Gupta, S. Varadarajan, W. Gomes, S. Hussain, H. Krishnamurthy, M. Venkateshmurthy, S. Jain
A System-Level Solution to Domino Synthesis with 2 GHz Application. ICCD (2002)
Prashant Saxena, Satyanarayan Gupta
Shield count minimization in congested regions. ISPD (2002)
Prashant Saxena, C. L. Liu
Optimization of the maximum delay of global interconnects duringlayer assignment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20 (4) (2001)
Ki-Wook Kim, Seong-Ook Jung, Prashant Saxena, C. L. Liu, Sung-Mo Kang
Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique. DAC (2001)
Prashant Saxena, C. L. Liu
A postprocessing algorithm for crosstalk-driven wire perturbation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (6) (2000)
Prashant Saxena, Peichen Pan, C. L. Liu
The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive Latches. VLSI Design (1999)
Prashant Saxena, C. L. Liu
Crosstalk Minimization Using Wire Perturbations. DAC (1999)
Prashant Saxena, C. L. Liu
A performance-driven layer assignment algorithm for multiple interconnect trees. ICCAD (1998)
Vamsi Boppana, Prashant Saxena, Prithviraj Banerjee, W. Kent Fuchs, C. L. Liu
A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs. Euro-Par, Vol. I (1996)
Aviezri S. Fraenkel, Edward M. Reingold, Prashant Saxena
Efficient Management of Dynamic Tables. Inf. Process. Lett. 50 (1) (1994)