Vamsi Boppana

Publication Activity (10 Years)

Years Active: 1993-2019
Publications (10 Years): 2

Top Topics

Software Implementation

Ai Technologies

Fpga Technology

Top Venues

Hot Chips Symposium

Publications

Sagheer Ahmad, Sridhar Subramanian, Vamsi Boppana, Shankar Lakka, Fu-Hing Ho, Tomai Knopp, Juanjo Noguera, Gaurav Singh, Ralph Wittig
Xilinx First 7nm Device: Versal AI Core (VC1902). Hot Chips Symposium (2019)
Sagheer Ahmad, Vamsi Boppana, Ilya Ganusov, Vinod Kathail, Vidya Rajagopalan, Ralph Wittig
A 16-nm Multiprocessing System-on-Chip Field-Programmable Gate Array Platform. IEEE Micro 36 (2) (2016)
Vamsi Boppana, Sagheer Ahmad, Ilya Ganusov, Vinod Kathail, Vidya Rajagopalan, Ralph Wittig
UltraScale+ MPSoC and FPGA families. Hot Chips Symposium (2015)
Vidya Rajagopalan, Vamsi Boppana, Sandeep Dutta, Brad Taylor, Ralph Wittig
Xilinx Zynq-7000 EPP: An extensible processing platform family. Hot Chips Symposium (2011)
Vamsi Boppana, Rahoul Varma, S. Balajee
Implementing the Best Processor Cores. VLSI Design (2008)
Shashank Bhonge, Vamsi Boppana
Low power chips: a fabless asic perspective. ISLPED (2008)
Rob Roy, Debashis Bhattacharya, Vamsi Boppana
Transistor-Level Optimization of Digital Designs with Flex Cells. Computer 38 (2) (2005)
Hiroaki Yoshida, Kaushik De, Vamsi Boppana
Accurate pre-layout estimation of standard cell characteristics. DAC (2004)
M. Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana
Fault equivalence identification in combinational circuits using implication and evaluation techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (7) (2003)
Indradeep Ghosh, Krishna Sekar, Vamsi Boppana
Design for Verification at the Register Transfer Level. VLSI Design (2002)
Srivaths Ravi, Indradeep Ghosh, Vamsi Boppana, Niraj K. Jha
Fault-diagnosis-based technique for establishing RTL and gate-levelcorrespondences. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20 (12) (2001)
Biplab K. Sikdar, Debesh K. Das, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee, Parimal Pal Chaudhuri
Cellular automata as a built in self test structure. ASP-DAC (2001)
M. Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana
Fault Equivalence Identification Using Redundancy Information and Static and Dynamic Extraction. VTS (2001)
Srivaths Ravi, Niraj K. Jha, Indradeep Ghosh, Vamsi Boppana
A Technique for Identifying RTL and Gate-Level Correspondences. ICCD (2000)
Biplab K. Sikdar, Kolin Paul, Gosta Pada Biswas, Parimal Pal Chaudhuri, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee
Theory and Application of GF(2p) Cellular Automata as On-chip Test Pattern Generator. VLSI Design (2000)
Vamsi Boppana, Indradeep Ghosh, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita
Hierarchical Error Diagnosis Targeting RTL Circuits. VLSI Design (2000)
Ankur Jain, Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Michael S. Hsiao
Testing, Verification, and Diagnosis in the Presence of Unknowns. VTS (2000)
Ankur Jain, Michael S. Hsiao, Vamsi Boppana, Masahiro Fujita
On the Evaluation of Arbitrary Defect Coverage of Test Sets. VTS (1999)
Vamsi Boppana, Sreeranga P. Rajan, Koichiro Takayama, Masahiro Fujita
Model Checking Based on Sequential ATPG. CAV (1999)
M. Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana
Implication and Evaluation Techniques for Proving Fault Equivalence. VTS (1999)
Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Pradeep Bollineni
Multiple Error Diagnosis Based on Xlists. DAC (1999)
Vamsi Boppana, Masahiro Fujita
Modeling the unknown! Towards model-independent fault and error diagnosis. ITC (1998)
Vamsi Boppana, W. Kent Fuchs
Dynamic fault collapsing and diagnostic test pattern generation for sequential circuits. ICCAD (1998)
Ismed Hartanto, Vamsi Boppana, Janak H. Patel, W. Kent Fuchs
Diagnostic Test Pattern Generation for Sequential Circuits. VTS (1997)
Vamsi Boppana, Ismed Hartanto, W. Kent Fuchs
Characterization and Implicit Identification of Sequential Indistinguishability. VLSI Design (1997)
Ismed Hartanto, Vamsi Boppana, W. Kent Fuchs
Identification of unsettable flip-flops for partial scan and faster ATPG. ICCAD (1996)
Vamsi Boppana, Prashant Saxena, Prithviraj Banerjee, W. Kent Fuchs, C. L. Liu
A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs. Euro-Par, Vol. I (1996)
Ismed Hartanto, Vamsi Boppana, W. Kent Fuchs
Diagnostic Fault Equivalence Identification Using Redundancy Information and Structural Analysis. ITC (1996)
Vamsi Boppana, W. Kent Fuchs
Integrated fault diagnosis targeting reduced simulation. ICCAD (1996)
Vamsi Boppana, Ismed Hartanto, W. Kent Fuchs
Fault Diagnosis Using State Information. FTCS (1996)
Vamsi Boppana, Ismed Hartanto, W. Kent Fuchs
Full fault dictionary storage based on labeled tree encoding. VTS (1996)
Vamsi Boppana, W. Kent Fuchs
Partial Scan Design Based on State Transition Modeling. ITC (1996)
Sukumar Nandi, Vamsi Boppana, Parimal Pal Chaudhuri
A CAD Tool for Design of On-Chip Store & Generate Scheme. VLSI Design (1994)
Vamsi Boppana, W. Kent Fuchs
Fault dictionary compaction by output sequence removal. ICCAD (1994)
Sukumar Nandi, Vamsi Boppana, Supratik Chakraborty, Parimal Pal Chaudhuri, Samir Roy
Delay Fault Test Generation with Cellular Automata. VLSI Design (1993)