Koichiro Takayama

Publication Activity (10 Years)

Years Active: 1988-2014
Publications (10 Years): 0

Top Topics

Class Imbalance

Software Defect Prediction

Ensemble Learning

Top Venues

Publications

Matthieu Parizy, Koichiro Takayama, Yuji Kanazawa
Software Defect Prediction for LSI Designs. ICSME (2014)
Praveen K. Murthy, Sreeranga P. Rajan, Koichiro Takayama
High level hardware validation using hierarchical message sequence charts. HLDVT (2004)
Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Jacob A. Abraham, Donald S. Fussell, Masahiro Fujita
Efficient Combinational Verification Using Overlapping Local BDDs and a Hash Table. Formal Methods Syst. Des. 21 (1) (2002)
Shuo Sheng, Koichiro Takayama, Michael S. Hsiao
Effective safety property checking using simulation-based sequential ATPG. DAC (2002)
Farzan Fallah, Koichiro Takayama
A New Functional Test Program Generation Methodology. ICCD (2001)
Subramanian Rajagopalan, Sreeranga P. Rajan, Sharad Malik, Sandro Rigo, Guido Araujo, Koichiro Takayama
A retargetable VLIW compiler framework for DSPs withinstruction-level parallelism. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20 (11) (2001)
Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita
Automatic partitioning for efficient combinatorial verification. ASP-DAC (2000)
Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell
An Efficient Filter-Based Approach for Combinational Verification. DATE (1999)
Vamsi Boppana, Sreeranga P. Rajan, Koichiro Takayama, Masahiro Fujita
Model Checking Based on Sequential ATPG. CAV (1999)
Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell
An efficient filter-based approach for combinational verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (11) (1999)
Koichiro Takayama, Taizo Satoh, Tsuneo Nakata, Fumiyasu Hirose
An approach to verify a large scale system-on-a-chip using symbolic model checking. ICCD (1998)
Fumiyasu Hirose, Koichiro Takayama, Nobuaki Kawato
A high-speed test-generation method using a test generation circuit. Systems and Computers in Japan 21 (11) (1990)
Fumiyasu Hirose, Koichiro Takayama, Nobuaki Kawato
A Method to Generate Tests for Combinational Logic Circuits Using an Ultra-High-Speed Logic Simulator. ITC (1988)