Fumiyasu Hirose

Publication Activity (10 Years)

Years Active: 1980-1999
Publications (10 Years): 0

Publications

Rajeev Murgai, Fumiyasu Hirose, Masahiro Fujita
Speeding Up Look-up-Table Driven Logic Simulation. VLSI (1999)
Koichiro Takayama, Taizo Satoh, Tsuneo Nakata, Fumiyasu Hirose
An approach to verify a large scale system-on-a-chip using symbolic model checking. ICCD (1998)
Minoru Shoji, Fumiyasu Hirose, Shintaro Shimogori, Satoshi Kowatari, Hiroshi Nagai
Acceleration of behavioral simulation on simulation specific machines. ED&TC (1997)
Masahiro Sano, Shintaro Shimogori, Fumiyasu Hirose
Acceleration of mincut partitioning using hardware CAD accelerator TP5000. ASP-DAC (1997)
Hiroaki Iwashita, Tsuneo Nakata, Fumiyasu Hirose
CTL model checking based on forward state traversal. ICCAD (1996)
Rajeev Murgai, Masahiro Fujita, Fumiyasu Hirose
Logic synthesis for a single large look-up table. ICCD (1995)
Vishwani D. Agrawal, Bernard Courtois, Fumiyasu Hirose, Sandip Kundu, Chung-Len Lee, Yinghua Min, P. Pal Chaudhuri
Panel: New Research Problems in the Emerging Test Technology. Asian Test Symposium (1995)
Hiroaki Iwashita, Satoshi Kowatari, Tsuneo Nakata, Fumiyasu Hirose
Automatic test program generation for pipelined processors. ICCAD (1994)
Yukiko Izuta, Fumiyasu Hirose
Test pattern generation system for delay faults using a high speed simulation processor 'SP'. VTS (1992)
Fumiyasu Hirose
Performance Evaluation of an Event-Driven Logic Simulation Machine. DAC (1992)
Fumiyasu Hirose, Koichiro Takayama, Nobuaki Kawato
A high-speed test-generation method using a test generation circuit. Systems and Computers in Japan 21 (11) (1990)
Hiroshi Yamada, Fumiyasu Hirose, Junichi Niitsuma, Tatsuya Shindo
Simulation processor "SP". Systems and Computers in Japan 20 (4) (1989)
Shigeru Takasaki, Fumiyasu Hirose, Akihiko Yamada
Logic simulation engines in Japan. IEEE Des. Test 6 (5) (1989)
Minoru Saitoh, Kenji Iwata, Akiko Nokamura, Makoto Kakegawa, Junichi Masuda, Hirofumi Hamamura, Fumiyasu Hirose, Nobuaki Kawato
Logic Simulation System Using Simulation Processor (SP). DAC (1988)
Fumiyasu Hirose, Koichiro Takayama, Nobuaki Kawato
A Method to Generate Tests for Combinational Logic Circuits Using an Ultra-High-Speed Logic Simulator. ITC (1988)
Hiroshi Shiraishi, Fumiyasu Hirose
Efficient placement and routing techniques for master slice LSI. DAC (1980)