ED&TC

Keyphrases

Publications

1997

John P. Fishburn
Shaping a VLSI wire to minimize Elmore delay. ED&TC (1997)
Ad J. van de Goor, Georgi Gaydadjiev, Vyacheslav N. Yarmolik, V. G. Mikitjuk
March LA: a test for linked memory faults. ED&TC (1997)
Hsiao-Ping Tseng, Carl Sechen
A gridless multi-layer router for standard cell circuits using CTM cells. ED&TC (1997)
Andreas Hett, Rolf Drechsler, Bernd Becker
Fast and efficient construction of BDDs by reordering based synthesis. ED&TC (1997)
J. Gonzalez-Torres, P. A. Mateos, J. M. Hernandez
Full custom chip set for high speed serial communications up to 2.48 Gbit/s. ED&TC (1997)
Pradip K. Jha, Nikil D. Dutt
Library mapping for memories. ED&TC (1997)
Stefan Hendricx, Luc J. M. Claesen
A symbolic core approach to the formal verification of integrated mixed-mode applications. ED&TC (1997)
Julio Faura, C. Horton, B. Krah, Joan Cabestany, M. A. Aguirre, Josep Maria Insenser
A new field programmable system-on-a-chip for mixed signal integration. ED&TC (1997)
Thomas Olbrich, Ian Andrew Grout, Y. Eben Aimine, Andrew Mark David Richardson, Jean-Noël Contensou
A new quality estimation methodology for mixed-signal and analogue ICs. ED&TC (1997)
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel
Sequential circuit test generation using dynamic state traversal. ED&TC (1997)
S. Turgis, Jean Michel Daga, Josep M. Portal, Daniel Auvergne
Internal power modelling and minimization in CMOS inverters. ED&TC (1997)
Vladimír Székely, Andras Pahi, András Poppe, Márta Rencz, Alpar Csendes
SISSSI-A tool for dynamic electro-thermal simulation of analog VLSI cells. ED&TC (1997)
Antonis M. Paschalis, Nikolaos Gaitanis, Dimitris Gizopoulos, Panagiotis Kostarakis
A totally self-checking 1-out-of-3 code error indicator. ED&TC (1997)
Jeroen A. J. Leijten, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess
PROPHID: a data-driven multi-processor architecture for high-performance DSP. ED&TC (1997)
Radim Cmar, Serge Vernalde
Highly scalable parallel parametrizable architecture of the motion estimator. ED&TC (1997)
Filip Thoen, J. Van Der Steen, Gjalt G. de Jong, Gert Goossens, Hugo De Man
Multi-thread graph: a system model for real-time embedded software synthesis. ED&TC (1997)
Kanad Chakraborty, Pinaki Mazumder
A programmable boundary scan technique for board-level, parallel functional duplex march testing of word-oriented multiport static RAMs. ED&TC (1997)
Anatol Ursu, Gabriela Gruita, Sergiu Zaporojan
Design and verification of the sequential systems automata using temporal logic specifications. ED&TC (1997)
Prasoon Surti, Liang-Fang Chao, Akhilesh Tyagi
Low power FSM design using Huffman-style encoding. ED&TC (1997)
Mehrdad Nourani, Christos A. Papachristou
Structural BIST insertion using behavioral test analysis. ED&TC (1997)
Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi
Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks. ED&TC (1997)
Yoshinobu Higami, Kozo Kinoshita
Design of partially parallel scan chain. ED&TC (1997)
Vikram Saxena, Farid N. Najm, Ibrahim N. Hajj
Monte-Carlo approach for power estimation in sequential circuits. ED&TC (1997)
Thorsten Grötker, Rainer Schoenen, Heinrich Meyr
PCC: a modeling technique for mixed control/data flow systems. ED&TC (1997)
E. K. F. Lee
Reconfigurable data converter as a building block for mixed-signal test. ED&TC (1997)
Ayman M. Wahba, Dominique Borrione
Connection error location and correction in combinational circuits. ED&TC (1997)
M. R. Karthikeyan, Soumitra Kumar Nandy
An asynchronous architecture for digital signal processors. ED&TC (1997)
Michele Favalli, Cecilia Metra
Testing scheme for IC's clocks. ED&TC (1997)
Stéphane Donnay, Georges G. E. Gielen, Willy M. C. Sansen, Wim Kruiskamp, Domine Leenaerts, W. van Bokhoven
High-level synthesis of analog sensor interface front-ends. ED&TC (1997)
Christian Dufaza, Yervant Zorian
On the generation of pseudo-deterministic two-patterns test sequence with LFSRs. ED&TC (1997)
Thomas Kropf, Jürgen Ruf
Using MTBDDs for discrete timed symbolic model checking. ED&TC (1997)
B. Laquai, H. Richter, H. Werkmann
A production-oriented measurement method for fast and exhaustive Iddq tests. ED&TC (1997)
Ignacio Garcia-Vargas, Mariano Galan, Francisco V. Fernández, Ángel Rodríguez-Vázquez
An algorithm for numerical reference generation in symbolic analysis of large analog circuits. ED&TC (1997)
Ricardo de Oliveira Duarte, Michael Nicolaidis, Hakim Bederr, Yervant Zorian
Fault-secure shifter design: results and implementations. ED&TC (1997)
Gianpiero Cabodi, Paolo Camurati, Luciano Lavagno, Stefano Quer
Verification and synthesis of counters based on symbolic techniques. ED&TC (1997)
Andre Hertwig, Hans-Joachim Wunderlich
Fast controllers for data dominated applications. ED&TC (1997)
Claus Schneider
A methodology for hardware architecture trade-off at different levels of abstraction. ED&TC (1997)
José T. de Sousa, Peter Y. K. Cheung
Improved diagnosis of realistic interconnect shorts. ED&TC (1997)
Ronald J. W. T. Tangelder, G. Diemel, Hans G. Kerkhoff
Smart sensor system application: an integrated compass. ED&TC (1997)
Miguel Miranda, M. Kaspar, Francky Catthoor, Hugo De Man
Architectural exploration and optimization for counter based hardware address generation. ED&TC (1997)
Rolf Drechsler, Harry Hengster, Horst Schäfer, Joachim Hartmann, Bernd Becker
Testability of 2-level AND/EXOR circuits. ED&TC (1997)
Guo-Neng Lu, Gerard Sou
A CMOS low-voltage, high-gain op-amp. ED&TC (1997)
B. Romanowicz, M. Laudon, P. Lerch, Philippe Renaud, Hans Peter Amann, A. Boegli, Vincent Moser, Fausto Pellandini
Modeling and simulation of electromechanical transducers in microsystems using an analog hardware description language. ED&TC (1997)
Le-Chin Eugene Liu, Carl Sechen
Multi-layer chip-level global routing using an efficient graph-based Steiner tree heuristic. ED&TC (1997)
Wim F. J. Verhaegh, Paul E. R. Lippens, Emile H. L. Aarts, Jef L. van Meerbergen
Multidimensional periodic scheduling: a solution approach. ED&TC (1997)
Chih-Tsun Huang, Cheng-Wen Wu
High-speed C-testable systolic array design for Galois-field inversion. ED&TC (1997)
Pierre Girodias, Eduard Cerny
Interface timing verification with delay correlation using constraint logic programming. ED&TC (1997)
M. Svajda, B. Straka, Hans A. R. Manhaeve
A monolithic off-chip IDDQ monitor. ED&TC (1997)
U. Geigenmüller, N. P. van der Meijs
Cartesian multipole based numerical integration for 3D capacitance extraction. ED&TC (1997)
Ronald D. Blanton, John P. Hayes
The input pattern fault model and its application. ED&TC (1997)