Akihiko Yamada

Publication Activity (10 Years)

Years Active: 1974-2023
Publications (10 Years): 5

Top Topics

Information Sciences

Electrical Engineering

Top Venues

IEEE Ann. Hist. Comput.

Publications

Akihiko Yamada, Satoshi Denno, Yafei Hou
Iterative User Scheduling Method for MU-MIMO-OFDM Systems. GCCE (2023)
Radomir S. Stankovic, Tsutomu Sasao, Jaakko T. Astola, Akihiko Yamada
Remarks on the Design of First Digital Computers in Japan - Contributions of Yasuo Komamiya. EUROCAST (1) (2019)
Akihiko Yamada
Parametron and Relay Computers Exhibition Held at Tokyo University of Science in November, 2018. IEEE Ann. Hist. Comput. 41 (1) (2019)
Akihiko Yamada
2018 NEC C&C Prize Ceremony. IEEE Ann. Hist. Comput. 41 (2) (2019)
Akihiko Yamada
IPSJ Certifies 100 IP Technology Heritage Artifacts in 10 Years. IEEE Ann. Hist. Comput. 40 (3) (2018)
Akihiko Yamada, Dag Spicer
Events and Sightings. IEEE Ann. Hist. Comput. 34 (3) (2012)
Chigusa Kita, Thomas Haigh, Dag Spicer, Akihiko Yamada, Thomas J. Misa
Events and Sightings. IEEE Ann. Hist. Comput. 30 (2) (2008)
Xian-Hua Han, Yen-Wei Chen, Akihiko Yamada, Hideto Fujita
Robust Face Recognition Based on Modified ICA without Training Sample of Test Subjects. IIH-MSP (2008)
Chigusa Kita, Dag Spicer, Anne Fitzpatrick, Akihiko Yamada
Events and Sightings. IEEE Ann. Hist. Comput. 29 (2) (2007)
Akihiko Yamada, Takeo Kanade
Multi-subregion-based probabilistic approach to pose-invariant face recognition. Systems and Computers in Japan 37 (8) (2006)
Takeo Kanade, Akihiko Yamada
Multi-subregion based probabilistic approach toward pose-invariant face recognition. CIRA (2003)
Shogo Muramatsu, Akihiko Yamada, Hitoshi Kiya
A design method of multidimensional linear-phase paraunitary filter banks with a lattice structure. IEEE Trans. Signal Process. 47 (3) (1999)
Shogo Muramatsu, Akihiko Yamada, Hitoshi Kiya
A design method OF 2-D axial-symmetric paraunitary filter banks with a lattice structure. EUSIPCO (1998)
K. Kajita, Hiroyuki Kobayashi, Shogo Muramatsu, Akihiko Yamada, Hitoshi Kiya
A design method for oversampled paraunitary DFT filter banks using householder factorization. EUSIPCO (1996)
Akihiko Yamada
Challenge of design and test of ultra-large-scale circuits. ITC (1990)
Akihiko Yamada
Design Automation for Large Mainframes and Supercomputers in NEC. IFIP Congress (1989)
Shigeru Takasaki, Fumiyasu Hirose, Akihiko Yamada
Logic simulation engines in Japan. IEEE Des. Test 6 (5) (1989)
Shigehiro Funatsu, Masato Kawai, Akihiko Yamada
Scan design at NEC. IEEE Des. Test 6 (3) (1989)
Minoru Nomura, Shinichi Sato, Nobuo Takano, Toshinori Aoyama, Akihiko Yamada
Timing verification system based on delay time hierarchical nature. DAC (1982)
Kazutoshi Takahashi, Etsuo Takahashi, Tatsushige Bitoh, Toshinori Aoyama, Akihiko Yamada
MDS: An improved total system for firmware development. MICRO (1982)
Akihiko Yamada
Design automation status in Japan. DAC (1981)
Tohru Sasaki, Akihiko Yamada, Toshinori Aoyama, Katsutoshi Hasegawa, Shunichi Kato, Shinichi Sato
Hierarchical design verification for large digital systems. DAC (1981)
Shigeru Takasaki, Masato Kawai, Shigehiro Funatsu, Akihiko Yamada
A Calculus of Testability Measure at the Functional Level. ITC (1981)
Tohru Sasaki, Akihiko Yamada, Shunichi Kato, Terufumi Nakazawa, Kyoji Tomita, Nobuyoshi Nomizu
MIXS: A mixed level simulator for large digital system logic verification. DAC (1980)
Akihiko Yamada, Nobuo Wakatsuki, T. Fukui, Shigehiro Funatsu
Automatic System Level Test Generation and Fault Location for Large Digital Systems. DAC (1978)
Akihiko Yamada, Nobuo Wakatsuki, Hideo Shibano, Osamu Itoh, Kyoji Tomita, Shigehiro Funatsu
Automatic test generation for large digital circuits. DAC (1977)
Akihiko Yamada, Akihiro Kawaguchi, Kazutoshi Takahashi, Shunichi Kato
Microprogramming Design support System. DAC (1974)