Vishwani D. Agrawal

ORCID

Publication Activity (10 Years)

Years Active: 1972-2024
Publications (10 Years): 73

Top Venues

Publications

Vishwani D. Agrawal
Editorial. J. Electron. Test. 40 (2) (2024)
Soham Roy, Spencer K. Millican, Vishwani D. Agrawal
A Survey and Recent Advances: Machine Intelligence in Electronic Testing. J. Electron. Test. 40 (2) (2024)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 40 (3) (2024)
Soham Roy, Vishwani D. Agrawal
An Amalgamated Testability Measure Derived from Machine Intelligence. VLSID (2024)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 40 (1) (2024)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 39 (4) (2023)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 39 (5) (2023)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 39 (2) (2023)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 39 (1) (2023)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 39 (3) (2023)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 38 (4) (2022)
Ziqi Zhou, Ujjwal Guin, Peng Li, Vishwani D. Agrawal
Fault Modeling and Test Generation for Technology-Specific Defects of Skyrmion Logic Circuits. VTS (2022)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 38 (3) (2022)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 38 (6) (2022)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 38 (1) (2022)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 38 (2) (2022)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 38 (5) (2022)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 37 (2) (2021)
Ziqi Zhou, Ujjwal Guin, Peng Li, Vishwani D. Agrawal
Defect Characterization and Testing of Skyrmion-Based Logic Circuits. VTS (2021)
Soham Roy, Spencer K. Millican, Vishwani D. Agrawal
Special Session - Machine Learning in Test: A Survey of Analog, Digital, Memory, and RF Integrated Circuits. VTS (2021)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 37 (4) (2021)
Soham Roy, Spencer K. Millican, Vishwani D. Agrawal
Unsupervised Learning in Test Generation for Digital Integrated Circuits. ETS (2021)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 37 (1) (2021)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 37 (5) (2021)
Prattay Chowdhury, Ujjwal Guin, Adit D. Singh, Vishwani D. Agrawal
Estimating Operational Age of an Integrated Circuit. J. Electron. Test. 37 (1) (2021)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 37 (3) (2021)
Soham Roy, Spencer K. Millican, Vishwani D. Agrawal
Training Neural Network for Machine Intelligence in Automatic Test Pattern Generator. VLSI Design (2021)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 36 (4) (2020)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 36 (3) (2020)
Vishwani D. Agrawal
Message from the Steering Committee Chair. VLSI Design (2020)
Soham Roy, Spencer K. Millican, Vishwani D. Agrawal
Machine Intelligence for Efficient Test Pattern Generation. ITC (2020)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 36 (1) (2020)
Yang Sun, Spencer K. Millican, Vishwani D. Agrawal
Special Session: Survey of Test Point Insertion for Logic Built-in Self-test. VTS (2020)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 36 (6) (2020)
Soham Roy, Brandon Stiene, Spencer K. Millican, Vishwani D. Agrawal
Improved Pseudo-Random Fault Coverage Through Inversions: a Study on Test Point Architectures. J. Electron. Test. 36 (1) (2020)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 36 (5) (2020)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 36 (2) (2020)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 35 (1) (2019)
Harshil Goyal, Vishwani D. Agrawal
Technology Characterization Model and Scaling for Energy Management. VDAT (2019)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 35 (6) (2019)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 35 (5) (2019)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 35 (3) (2019)
Jubayer Mahmod, Spencer K. Millican, Ujjwal Guin, Vishwani D. Agrawal
Special Session: Delay Fault Testing - Present and Future. VTS (2019)
Soham Roy, Brandon Stiene, Spencer K. Millican, Vishwani D. Agrawal
Improved Random Pattern Delay Fault Coverage Using Inversion Test Points. NATW (2019)
Prattay Chowdhury, Ujjwal Guin, Adit D. Singh, Vishwani D. Agrawal
Two-Pattern ∆IDDQ Test for Recycled IC Detection. VLSI Design (2019)
Spencer K. Millican, Yang Sun, Soham Roy, Vishwani D. Agrawal
Applying Neural Networks to Delay Fault Testing: Test Point Insertion and Random Circuit Training. ATS (2019)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 35 (2) (2019)
Mustafa M. Shihab, Vishwani D. Agrawal
Energy Efficient Power Distribution on Many-Core SoC. VLSI Design (2019)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 35 (4) (2019)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 34 (3) (2018)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 34 (5) (2018)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 34 (4) (2018)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 34 (1) (2018)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 34 (2) (2018)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 34 (6) (2018)
Ziqi Zhou, Ujjwal Guin, Vishwani D. Agrawal
Modeling and test generation for combinational hardware Trojans. VTS (2018)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 33 (2) (2017)
Vijay Sheshadri, Vishwani D. Agrawal, Prathima Agrawal
Power-Aware Optimization of SoC Test Schedules Using Voltage and Frequency Scaling. J. Electron. Test. 33 (2) (2017)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 33 (6) (2017)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 33 (1) (2017)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 33 (4) (2017)
Bei Zhang, Vishwani D. Agrawal
Three-Stage Optimization of Pre-Bond Diagnosis of TSV Defects. J. Electron. Test. 33 (5) (2017)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 33 (3) (2017)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 33 (5) (2017)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 32 (1) (2016)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 32 (2) (2016)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 32 (6) (2016)
Muralidharan Venkatasubramanian, Vishwani D. Agrawal
Database Search and ATPG - Interdisciplinary Domains and Algorithms. VLSI Design (2016)
Muralidharan Venkatasubramanian, Vishwani D. Agrawal
Failures Guide Probabilistic Search for a Hard-to-Find Test. NATW (2016)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 32 (4) (2016)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 32 (3) (2016)
Baohu Li, Vishwani D. Agrawal
Applications of Mixed-Signal Technology in Digital Testing. J. Electron. Test. 32 (2) (2016)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 32 (5) (2016)
Harshit Goyal, Vishwani D. Agrawal
Characterizing Processors for Energy and Performance Management. MTV (2015)
Suraj Sindia, Vishwani D. Agrawal
Defect Level Constrained Optimization of Analog and Radio Frequency Specification Tests. J. Electron. Test. 31 (5-6) (2015)
Sindhu Gunasekar, Vishwani D. Agrawal
Few Good Frequencies for Power-Constrained Test. VLSI Design (2015)
Víctor H. Champac, Yervant Zorian, Letícia Maria Bolzani Pöhls, Vishwani D. Agrawal
Message from the LATS2015 Chairs. LATS (2015)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 31 (1) (2015)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 31 (4) (2015)
Baohu Li, Bei Zhang, Vishwani D. Agrawal
Adopting multi-valued logic for reduced pin-count testing. LATS (2015)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 31 (5-6) (2015)
Huiting Zhang, Vishwani D. Agrawal
SoC TAM Design to Minimize Test Application Time. NATW (2015)
Sindhu Gunasekar, Vishwani D. Agrawal
A Maximum Power Algorithm to Find Frequencies for Aperiodic Clock Testing. J. Electron. Test. 31 (4) (2015)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 31 (3) (2015)
Bei Zhang, Vishwani D. Agrawal
Diagnostic Tests for Pre-bond TSV Defects. VLSI Design (2015)
Muralidharan Venkatasubramanian, Vishwani D. Agrawal, James J. Janaher
Quest for a quantum search algorithm for testing stuck-at faults in digital circuits. DFTS (2015)
Baohu Li, Vishwani D. Agrawal
Multivalued Logic for Reduced Pin Count and Multi-site SoC Testing. NATW (2015)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 31 (2) (2015)
Hejia Liu, Vishwani D. Agrawal
Securing IEEE 1687-2014 Standard Instrumentation Access by LFSR Key. ATS (2015)
Bei Zhang, Vishwani D. Agrawal
An optimized diagnostic procedure for pre-bond TSV defects. ICCD (2014)
Muralidharan Venkatasubramanian, Vishwani D. Agrawal
A New Test Vector Search Algorithm for a Single Stuck-at Fault Using Probabilistic Correlation. NATW (2014)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 30 (2) (2014)
Yu Zhang, Bei Zhang, Vishwani D. Agrawal
Diagnostic Test Generation for Transition Delay Faults Using Stuck-At Fault Detection Tools. J. Electron. Test. 30 (6) (2014)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 30 (6) (2014)
Praveen Venkataramani, Suraj Sindia, Vishwani D. Agrawal
A Test Time Theorem and its Applications. J. Electron. Test. 30 (2) (2014)
Suraj Sindia, Vishwani D. Agrawal
Specification test minimization for given defect level. LATW (2014)
Karthik Naishathrala Jayaraman, Vishwani D. Agrawal
A Four-Transistor Level Converter for Dual-Voltage Low-Power Design. J. Low Power Electron. 10 (4) (2014)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 30 (5) (2014)
Vishwani D. Agrawal
Editorial. J. Electron. Test. 30 (3) (2014)
Bei Zhang, Vishwani D. Agrawal
A Novel Wafer Manipulation Method for Yield Improvement and Cost Reduction of 3D Wafer-on-Wafer Stacked ICs. J. Electron. Test. 30 (1) (2014)

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Publication Activity (10 Years)

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Vishwani D. Agrawal