Suraj Sindia

Publication Activity (10 Years)

Years Active: 2009-2015
Publications (10 Years): 0

Top Topics

Innovative Ideas

Radio Frequency

Constrained Optimization

Educational Practices

Top Venues

J. Electron. Test.

Publications

Suraj Sindia, Vishwani D. Agrawal
Defect Level Constrained Optimization of Analog and Radio Frequency Specification Tests. J. Electron. Test. 31 (5-6) (2015)
Suraj Sindia
Innovative practices session 2C: New technologies, new challenges - 2. VTS (2015)
Praveen Venkataramani, Suraj Sindia, Vishwani D. Agrawal
A Test Time Theorem and its Applications. J. Electron. Test. 30 (2) (2014)
Suraj Sindia, Vishwani D. Agrawal
Specification test minimization for given defect level. LATW (2014)
Suraj Sindia, Vishwani D. Agrawal
Neural Network Guided Spatial Fault Resilience in Array Processors. J. Electron. Test. 29 (4) (2013)
Praveen Venkataramani, Suraj Sindia, Vishwani D. Agrawal
A test time theorem and its applications. LATW (2013)
Suraj Sindia, Vishwani D. Agrawal
High sensitivity test signatures for unconventional analog circuit test paradigms. ITC (2013)
Praveen Venkataramani, Suraj Sindia, Vishwani D. Agrawal
Finding best voltage and frequency to shorten power-constrained test time. VTS (2013)
Suraj Sindia, Fa Foster Dai, Vishwani D. Agrawal, Virendra Singh
Impact of process variations on computers used for image processing. ISCAS (2012)
Suraj Sindia, Vishwani D. Agrawal, Virendra Singh
Parametric Fault Testing of Non-Linear Analog Circuits Based on Polynomial and V-Transform Coefficients. J. Electron. Test. 28 (5) (2012)
Suraj Sindia, Vishwani D. Agrawal, Virendra Singh
Defect Level and Fault Coverage in Coefficient Based Analog Circuit Testing. J. Electron. Test. 28 (4) (2012)
Suraj Sindia, Vishwani D. Agrawal
Tailoring Tests for Functional Binning of Integrated Circuits. Asian Test Symposium (2012)
Suraj Sindia, Vishwani D. Agrawal
Towards spatial fault resilience in array processors. VTS (2012)
Suraj Sindia, Vishwani D. Agrawal, Virendra Singh
Testing linear and non-linear analog circuits using moment generating functions. LATW (2011)
Suraj Sindia, Vishwani D. Agrawal, Virendra Singh
Non-linear analog circuit test and diagnosis under process variation using V-Transform coefficients. VTS (2011)
Suraj Sindia, Vishwani D. Agrawal, Virendra Singh
Test and Diagnosis of Analog Circuits Using Moment Generating Functions. Asian Test Symposium (2011)
Suraj Sindia, Virendra Singh, Vishwani D. Agrawal
Parametric Fault Diagnosis of Nonlinear Analog Circuits Using Polynomial Coefficients. VLSI Design (2010)
Suraj Sindia, Virendra Singh, Vishwani D. Agrawal
Multi-tone Testing of Linear and Nonlinear Analog Circuits Using Polynomial Coefficients. Asian Test Symposium (2009)
Suraj Sindia, Virendra Singh, Vishwani D. Agrawal
Polynomial coefficient based DC testing of non-linear analog circuits. ACM Great Lakes Symposium on VLSI (2009)