Virendra Singh

ORCID

Publication Activity (10 Years)

Years Active: 2003-2024
Publications (10 Years): 91

Top Venues

Publications

Aditi Gupta, Adeiza James Onumanyi, Satyadev Ahlawat, Yamuna Prasad, Virendra Singh, Adnan M. Abu-Mahfouz
DAT: A robust Discriminant Analysis-based Test of unimodality for unknown input distributions. Pattern Recognit. Lett. 182 (2024)
Aditi Gupta, Sukanya Gupta, Adeiza James Onumanyi, Satyadev Ahlawat, Yamuna Prasad, Virendra Singh
A-TSPD: autonomous-two stage algorithm for robust peak detection in online time series. Clust. Comput. 27 (4) (2024)
Prakhar Diwan, Suryakant Toraskar, Varun Venkitaraman, Nirmal Kumar Boran, Chandramani Chaudhary, Virendra Singh
MIST: Many-ISA Scheduling Technique for Heterogeneous-ISA Architectures. VLSID (2024)
Virendra Singh, Mahendra Pratap Singh, Saumya Hegde, Maanak Gupta
Security in 5G Network Slices: Concerns and Opportunities. IEEE Access 12 (2024)
Chandramani Chaudhary, Nirmal Kumar Boran, N. Sangeeth, Virendra Singh
GNNDLD: Graph Neural Network with Directional Label Distribution. ICAART (2) (2024)
Sarath Babu, Virendra Singh
BD-MDLC: Behavior description-based enhanced malware detection for windows environment using longformer classifier. Comput. Secur. 146 (2024)
Raj Kumar Choudhary, Janeel Patel, Virendra Singh
Early Execution for Soft Error Detection. VLSID (2024)
Raghunandana K. K, Yogesh Prasad K. R, Matteo Sonza Reorda, Virendra Singh
TCC: GPGPU Architecture for Instruction Decoder and Control Flow Error Detection. DDECS (2024)
Pooja Choudhary, Lava Bhargava, Masahiro Fujita, Virendra Singh
LUT-based Arithmetic Circuit Approximation with Formal Guarantee on Worst Case Relative Error. LATS (2023)
Govind Rajhans Jadhav, Sonali Shukla, Virendra Singh
On Attacking Scan-based Logic Locking Schemes. DFT (2023)
Gowthami Konganapalle, Sonali Shukla, Virendra Singh
SMASh: A State Encoding Methodology Against Attacks on Finite State Machines. ATS (2023)
Raj Kumar Choudhary, Janeel Patel, Virendra Singh
ERrOR: Improving Performance and Fault Tolerance Using Early Execution. IOLTS (2023)
Raghunandana K. K, Yogesh Prasad K. R, Matteo Sonza Reorda, Virendra Singh
DDSR: An Online GPGPU Instruction Decoder Error Detecting and Correcting Architecture. DFT (2023)
Prokash Ghosh, Yogesh Gholap, Virendra Singh
On-Chip SRAM Disclosure Attack Prevention Technique for SoC. IOLTS (2023)
Tikaram Sanyashi, Nirmal Kumar Boran, Virendra Singh
Secure KNN Computation on Cloud. ICISS (2023)
Aditi Gupta, Adeiza James Onumanyi, Satyadev Ahlawat, Yamuna Prasad, Virendra Singh
TSPD: A Robust Online Time Series Two-Stage Peak Detection Algorithm. SOSE (2023)
Raghunandana K. K, B. K. S. V. L. Varaprasad, Matteo Sonza Reorda, Virendra Singh
TREFU: An Online Error Detecting and Correcting Fault Tolerant GPGPU Architecture. IOLTS (2023)
Pooja Choudhary, Lava Bhargava, G. U. Vinod, Ashok Kumar Suhag, Masahiro Fujita, Virendra Singh
Optimization of Imprecise Multiplier Circuits by using Binary Decision Diagram. iSES (2023)
Sonali Shukla, Bhavika Ranjeet Kumar, Virendra Singh
SSSN: Secured Streaming Scan Network. LATS (2023)
Raghunandana K. K, B. K. S. V. L. Varaprasad, Matteo Sonza Reorda, Virendra Singh
REFU: Redundant Execution with Idle Functional Units, Fault Tolerant GPGPU architecture. ISVLSI (2022)
Nirmal Kumar Boran, Pranil Joshi, Virendra Singh
PASS-P: Performance and Security Sensitive Dynamic Cache Partitioning. SECRYPT (2022)
Pooja Choudhary, Lava Bhargava, Masahiro Fujita, Virendra Singh
Synthesis of LUT Based Approximating Adder Circuits with Formal Error Guarantees. VDAT (2022)
Anishetti Venkatesh, Chandan Kumar Jha, G. U. Vinod, Masahiro Fujita, Virendra Singh
Scalable Construction of Formal Error Guaranteed LUT-Based Approximate Multipliers with Analytical Worst-Case Error Bound. VDAT (2022)
Ashwin Sanjay Lele, Srivatsava Jandhyala, Saurabh Gangurde, Virendra Singh, Sreenivas Subramoney, Udayan Ganguly
Disrupting Low-Write-Energy vs. Fast-Read Dilemma in RRAM to Enable L1 Instruction Cache. VDAT (2022)
Riccardo Cantoro, Francesco Garau, Riccardo Masante, Sandro Sartoni, Virendra Singh, Matteo Sonza Reorda
Exploiting post-silicon debug hardware to improve the fault coverage of Software Test Libraries. VTS (2022)
Pooja Choudhary, Lava Bhargava, Masahiro Fujita, Virendra Singh, Ashok Kumar Suhag
Approximating Arithmetic Circuits for IoT Devices Data Processing. Comput. Ind. Eng. 174 (2022)
Nirmal Kumar Boran, Shubhankit Rathore, Meet Udeshi, Virendra Singh
Fine-Grained Scheduling in Heterogeneous-ISA Architectures. IEEE Comput. Archit. Lett. 20 (1) (2021)
Vedant Satav, Virendra Singh
Locality-based Graph Reordering for Processing Speed-Ups and Impact of Diameter. CoRR (2021)
Harsh Bhargav, Vineesh V. S., Binod Kumar, Virendra Singh
Enhancing Testbench Quality via Genetic Algorithm. MWSCAS (2021)
V. S. Vineesh, Binod Kumar, Rushikesh Shinde, Neelam Sharma, Masahiro Fujita, Virendra Singh
Enhanced Design Debugging With Assistance From Guidance-Based Model Checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (5) (2021)
Winnie Thomas, Suryakant Toraskar, Virendra Singh
Dynamic Optimizations in GPU Using Roofline Model. ISCAS (2021)
Abhinish Anand, Winnie Thomas, Suryakant Toraskar, Virendra Singh
Predictive Warp Scheduling for Efficient Execution in GPGPU. ACM Great Lakes Symposium on VLSI (2021)
Jaynarayan T. Tudu, Satyadev Ahlawat, Sonali Shukla, Virendra Singh
A Framework for Configurable Joint-Scan Design-for-Test Architecture. J. Electron. Test. 37 (5) (2021)
Arindam Sarkar, Newton Singh, Varun Venkitaraman, Virendra Singh
DAM: Deadblock Aware Migration Techniques for STT-RAM-Based Hybrid Caches. IEEE Comput. Archit. Lett. 20 (1) (2021)
Insha Amin, Deepak Mishra, Ravikant Saini, Virendra Singh
Secrecy Rate Maximization at Near User in Untrusted NOMA with Trusted DF Relay. ANTS (2021)
Binod Kumar, Jay Adhaduk, Kanad Basu, Masahiro Fujita, Virendra Singh
A Methodology to Capture Fine-Grained Internal Visibility During Multisession Silicon Debug. IEEE Trans. Very Large Scale Integr. Syst. 28 (4) (2020)
Antara Ganguly, Shankar Balachandran, Anant V. Nori, Virendra Singh, Sreenivas Subramoney
Characterization of Data Generating Neural Network Applications on x86 CPU Architecture. ISPASS (2020)
Vinod G. U, Vineesh V. S., Jaynarayan T. Tudu, Masahiro Fujita, Virendra Singh
LUT-based Circuit Approximation with Targeted Error Guarantees. ATS (2020)
Binod Kumar, Swapniel Thakur, Kanad Basu, Masahiro Fujita, Virendra Singh
A Low Overhead Methodology for Validating Memory Consistency Models in Chip Multiprocessors. VLSI Design (2020)
Newton, Virendra Singh, Trevor E. Carlson
PIM-GraphSCC: PIM-Based Graph Processing Using Graph's Community Structures. IEEE Comput. Archit. Lett. 19 (2) (2020)
Binod Kumar, Kanad Basu, Masahiro Fujita, Virendra Singh
Post-Silicon Gate-Level Error Localization With Effective and Combined Trace Signal Selection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (1) (2020)
Shoba Gopalakrishnan, Virendra Singh
Soft-error reliable architecture for future microprocessors. IET Comput. Digit. Tech. 13 (3) (2019)
Binod Kumar, Masahiro Fujita, Virendra Singh
A Methodology for SAT-Based Electrical Error Debugging During Post-Silicon Validation. VLSI Design (2019)
Vineesh V. S., Binod Kumar, Rushikesh Shinde, Akshay Jaiswal, Harsh Bhargava, Virendra Singh
Orion: A Technique to Prune State Space Search Directions for Guidance-Based Formal Verification. ATS (2019)
Binod Kumar, Masahiro Fujita, Virendra Singh
SAT-based Silicon Debug of Electrical Errors under Restricted Observability Enhancement. J. Electron. Test. 35 (5) (2019)
Binod Kumar, Atul Kumar Bhosale, Masahiro Fujita, Virendra Singh
Validating Multi-Processor Cache Coherence Mechanisms under Diminished Observability. ATS (2019)
Antara Ganguly, Rajeev Muralidhar, Virendra Singh
Towards Energy Efficient non-von Neumann Architectures for Deep Learning. ISQED (2019)
Satyadev Ahlawat, Jaynarayan T. Tudu, Manoj Singh Gaur, Masahiro Fujita, Virendra Singh
Preventing Scan Attack through Test Response Encryption. DFT (2019)
Satyadev Ahlawat, Kailash Ahirwar, Jaynarayan T. Tudu, Masahiro Fujita, Virendra Singh
Securing Scan through Plain-text Restriction. IOLTS (2019)
Jaidev Shenoy, Kelly Ockunzzi, Virendra Singh, Kushal Kamal
On-chip MISR Compaction Technique to Reduce Diagnostic Effort and Test Time. VLSI Design (2019)
Raj Kumar Choudhary, Newton Singh, Harideep Nair, Rishabh Rawat, Virendra Singh
Freeflow Core: Enhancing Performance of In-Order Cores with Energy Efficiency. ICCD (2019)
Darshit Vaghani, Satyadev Ahlawat, Jaynarayan T. Tudu, Masahiro Fujita, Virendra Singh
On Securing Scan Design Through Test Vector Encryption. ISCAS (2018)
Satyadev Ahlawat, Darshit Vaghani, Naveen Bazard, Virendra Singh
Using MISR as Countermeasure Against Scan-Based Side-Channel Attacks. EWDTS (2018)
Toral Shah, Anzhela Yu. Matrosova, Masahiro Fujita, Virendra Singh
Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design. J. Electron. Test. 34 (1) (2018)
Rohini Gulve, Virendra Singh
ATPG power guards: On limiting the test power below threshold. DATE (2018)
Binod Kumar, Kanad Basu, Virendra Singh
A Technique for Electrical Error Localization with Learning Methods During Post-silicon Debugging. IGSC (2018)
Ankit Jindal, Binod Kumar, Nitish Jindal, Masahiro Fujita, Virendra Singh
Silicon Debug with Maximally Expanded Internal Observability Using Nearest Neighbor Algorithm. ISVLSI (2018)
Sandeep Goyal, Ron Joseph, Virendra Singh, Shalabh Gupta
A PAM-4 10S/12S line coding scheme with equi-probable levels. ISCAS (2018)
Antara Ganguly, Virendra Singh, Rajeev Muralidhar, Masahiro Fujita
Memory-system requirements for convolutional neural networks. MEMSYS (2018)
Nihar Hage, Satyadev Ahlawat, Virendra Singh
In-situ Monitoring for Slack Time Violation Without Performance Penalty. ISCAS (2018)
Suhit Pai, Newton Singh, Virendra Singh
AB-Aware: Application Behavior Aware Management of Shared Last Level Caches. ACM Great Lakes Symposium on VLSI (2018)
Toral Shah, Anzhela Yu. Matrosova, Binod Kumar, Masahiro Fujita, Virendra Singh
Testing multiple stuck-at faults of ROBDD based combinational circuit design. LATS (2017)
Newton, Sujit Kr Mahto, Suhit Pai, Virendra Singh
DAAIP: Deadblock Aware Adaptive Insertion Policy for High Performance Caching. ICCD (2017)
Nihar Hage, Rohini Gulve, Masahiro Fujita, Virendra Singh
On Testing of Superscalar Processors in Functional Mode for Delay Faults. VLSI Design (2017)
Binod Kumar, Ankit Jindal, Masahiro Fujita, Virendra Singh
Post-silicon observability enhancement with topology based trace signal selection. LATS (2017)
Nihar Hage, Rohini Gulve, Masahiro Fujita, Virendra Singh
Instruction-based self-test for delay faults maximizing operating temperature. IOLTS (2017)
Binod Kumar, Kanad Basu, Ankit Jindal, Masahiro Fujita, Virendra Singh
Improving post-silicon error detection with topological selection of trace signals. VLSI-SoC (2017)
Binod Kumar, Kanad Basu, Masahiro Fujita, Virendra Singh
RTL level trace signal selection and coverage estimation during post-silicon validation. HLDVT (2017)
Satyadev Ahlawat, Darshit Vaghani, Rohini Gulve, Virendra Singh
A low cost technique for scan chain diagnosis. ISCAS (2017)
Satyadev Ahlawat, Darshit Vaghani, Jaynarayan T. Tudu, Virendra Singh
On Securing Scan Design from Scan-Based Side-Channel Attacks. ATS (2017)
Binod Kumar, Ankit Jindal, Masahiro Fujita, Virendra Singh
Combining Restorability and Error Detection Ability for Effective Trace Signal Selection. ACM Great Lakes Symposium on VLSI (2017)
Abhishek Rajgadia, Newton, Virendra Singh
EEAL: Processors' Performance Enhancement Through Early Execution of Aliased Loads. ACM Great Lakes Symposium on VLSI (2017)
Satyadev Ahlawat, Darshit Vaghani, Virendra Singh
An efficient test technique to prevent scan-based side-channel attacks. ETS (2017)
Binod Kumar, Ankit Jindal, Virendra Singh, Masahiro Fujita
A Methodology for Trace Signal Selection to Improve Error Detection in Post-Silicon Validation. VLSI Design (2017)
Ankush Srivastava, Virendra Singh, Adit D. Singh, Kewal K. Saluja
Identifying high variability speed-limiting paths under aging. LATS (2017)
Binod Kumar, Ankit Jindal, Jaynarayan T. Tudu, Brajesh Pandey, Virendra Singh
Revisiting random access scan for effective enhancement of post-silicon observability. IOLTS (2017)
Ankush Srivastava, Virendra Singh, Adit D. Singh, Kewal K. Saluja
A Reliability-Aware Methodology to Isolate Timing-Critical Paths under Aging. J. Electron. Test. 33 (6) (2017)
Ankush Srivastava, Adit D. Singh, Virendra Singh, Kewal K. Saluja
Exploiting path delay test generation to develop better TDF tests for small delay defects. ITC (2017)
Shoba Gopalakrishnan, Virendra Singh
REMORA: A hybrid low-cost soft-error reliable fault tolerant architecture. DFT (2017)
Toral Shah, Anzhela Yu. Matrosova, Virendra Singh
Test pattern generation to detect multiple faults in ROBDD based combinational circuits. IOLTS (2017)
V. S. Vineesh, Nihar Hage, B. Karthik, Virendra Singh
Achieving full functional coverage for the forwarding unit of pipelined processors. EWDTS (2017)
Rohini Gulve, Anshu Goel, Virendra Singh
PHP: Power hungry pattern generation at higher abstraction level. EWDTS (2017)
Satyadev Ahlawat, Darshit Vaghani, Virendra Singh
Preventing scan-based side-channel attacks through key masking. DFT (2017)
Binod Kumar, Ankit Jindal, Virendra Singh
A trace signal selection algorithm for improved post-silicon debug. EWDTS (2016)
Shoba Gopalakrishnan, Virendra Singh
REMO: Redundant execution with minimum area, power, performance overhead fault tolerant architecture. IOLTS (2016)
Satyadev Ahlawat, Jaynarayan T. Tudu, Anzhela Yu. Matrosova, Virendra Singh
A high performance scan flip-flop design for serial and mixed mode scan test. IOLTS (2016)
Satyadev Ahlawat, Darshit Vaghani, Rohini Gulve, Virendra Singh
Enabling LOS delay test with slow scan enable. EWDTS (2016)
Nirmal Kumar Boran, Rameshwar Prasad Meghwal, Kuldeep Sharma, Binod Kumar, Virendra Singh
Performance modelling of heterogeneous ISA multicore architectures. EWDTS (2016)
Toral Shah, Virendra Singh, Anzhela Yu. Matrosova
ROBDD based path delay fault testable combinational circuit synthesis. EWDTS (2016)
Rohini Gulve, Virendra Singh
ILP based don't care bits filling technique for reducing capture power. EWDTS (2016)
Binod Kumar, Boda Nehru, Brajesh Pandey, Virendra Singh, Jaynarayan T. Tudu
A technique for low power, stuck-at fault diagnosable and reconfigurable scan architecture. EWDTS (2016)
Satyadev Ahlawat, Jaynarayan T. Tudu, Anzhela Yu. Matrosova, Virendra Singh
A New Scan Flip Flop Design to Eliminate Performance Penalty of Scan. ATS (2015)
Parth Lathigara, Shankar Balachandran, Virendra Singh
Application behavior aware re-reference interval prediction for shared LLC. ICCD (2015)
Toral Shah, Anzhela Yu. Matrosova, Virendra Singh
PDF testability of a combinational circuit derived by covering ROBDD nodes using Invert-And-Or circuits. VDAT (2015)
Virendra Singh, Adit D. Singh, Kewal K. Saluja
A Methodology for Identifying High Timing Variability Paths in Complex Designs. ATS (2015)
Adithyalal P. M, Shankar Balachandran, Virendra Singh
A Soft Error Resilient Low Leakage SRAM Cell Design. ATS (2015)
Nahit Pawar, Madhu N. Belur, Mani Bhushan, A. P. Tiwari, M. G. Kelkar, M. Pramanik, Virendra Singh
A data-driven adaptive model-identification based large-scale sensor management system: Application to self powered neutron detectors. EAIS (2014)
Lokesh Siddhu, Amit Mishra, Virendra Singh
Operand Isolation with Reduced Overhead for Low Power Datapath Design. VLSI Design (2014)
Indira Rawat, M. K. Gupta, Virendra Singh
Temperature aware test scheduling by modified floorplanning. EWDTS (2014)
Anzhela Yu. Matrosova, Sergey Ostanin, Irina Kirienko, Virendra Singh
Partially programmable circuit design. EWDTS (2014)

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Publication Activity (10 Years)

Top Topics

Top Venues

Virendra Singh