Anzhela Yu. Matrosova

Publication Activity (10 Years)

Years Active: 2000-2022
Publications (10 Years): 20

Top Topics

Boolean Functions

Top Venues

Autom. Remote. Control.

Publications

Andrey Laputenko, Nina Yevtushenko, Valentina Andreeva, Anzhela Yu. Matrosova
Deriving FSM-based tests using $a, b-\text{faults}$ for Logic Circuits. ISVLSI (2022)
Anzhela Yu. Matrosova, V. Provkin
Applying Incompletely Specified Boolean Functions for Patch Circuit Generation. EWDTS (2021)
Anzhela Yu. Matrosova, Semen Chernyshov, O. Kh. Kim, Ekaterina Nikolaeva
Constructing a Sequence Detecting Robustly Testable Path Delay Faults in Sequential Circuits. Autom. Remote. Control. 82 (11) (2021)
Anzhela Yu. Matrosova, V. Provkin
Masking Internal Node Logical Faults and Trojan Circuits Injections with Using SAT Solvers. AQTR (2020)
Anzhela Yu. Matrosova, Sergei Ostanin, Semen Chernyshov
Masking Robust Testable PDFs. EWDTS (2019)
Anzhela Yu. Matrosova, V. Provkin, Ekaterina Nikolaeva
Masking Internal Node Faults and Trojan Circuits in Logical Circuits. EWDTS (2019)
Toral Shah, Anzhela Yu. Matrosova, Masahiro Fujita, Virendra Singh
Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design. J. Electron. Test. 34 (1) (2018)
Anzhela Yu. Matrosova, Sergei Ostanin, Semen Chernyshov
Finding False Paths for Sequential Circuits Using Operations on ROBDDs. IOLTS (2018)
Anzhela Yu. Matrosova, Sergey Ostanin
Trojan circuits masking and debugging of combinational circuits with LUT insertion. AQTR (2018)
Toral Shah, Anzhela Yu. Matrosova, Binod Kumar, Masahiro Fujita, Virendra Singh
Testing multiple stuck-at faults of ROBDD based combinational circuit design. LATS (2017)
Anzhela Yu. Matrosova, Eugeniy Mitrofanov, Sergei Ostanin, Irina Kirienko
Preventing and masking Trojan circuits triggering out of working area. ECCTD (2017)
Anzhela Yu. Matrosova, Sergey Ostanin, D. Tretyakov, Natalia Butorina
Logic circuit design with gates, LUTs and MUXs oriented to mask faults. EWDTS (2017)
Anzhela Yu. Matrosova, Eugeniy Mitrofanov, Sergey Ostanin, Ekaterina Nikolaeva
Detection and masking of Trojan Circuits in sequential logic. EWDTS (2017)
Toral Shah, Anzhela Yu. Matrosova, Virendra Singh
Test pattern generation to detect multiple faults in ROBDD based combinational circuits. IOLTS (2017)
Anzhela Yu. Matrosova, Sergey Ostanin, Irina Kirienko, Ekaterina Nikolaeva
A fault-tolerant sequential circuit design for SAFs and PDFs soft errors. IOLTS (2016)
Anzhela Yu. Matrosova, Eugeniy Mitrofanov
Pseudo-exhaustive testing of sequential circuits for multiple stuck-at faults. EWDTS (2016)
Satyadev Ahlawat, Jaynarayan T. Tudu, Anzhela Yu. Matrosova, Virendra Singh
A high performance scan flip-flop design for serial and mixed mode scan test. IOLTS (2016)
Sergey Ostanin, Anzhela Yu. Matrosova, Natalia Butorina, V. Lavrov
A fault-tolerant sequential circuit design for soft errors based on fault-secure circuit. EWDTS (2016)
Toral Shah, Virendra Singh, Anzhela Yu. Matrosova
ROBDD based path delay fault testable combinational circuit synthesis. EWDTS (2016)
Anzhela Yu. Matrosova, Valentina Andreeva, Alexey Melnikov
ROBDDs application for finding the shortest transfer sequence of sequential circuit or only revealing existence of this sequence without deriving the sequence itself. EWDTS (2016)
Anzhela Yu. Matrosova, Sergey Ostanin, Irina Kirienko, Ekaterina Nikolaeva
Fault-tolerant high performance scheme design. EWDTS (2015)
Anzhela Yu. Matrosova, Eugeniy Mitrofanov, Toral Shah
Multiple stuck-at fault testability of a combinational circuit derived by covering ROBDD nodes by Invert-And-Or sub-circuits. EWDTS (2015)
Anzhela Yu. Matrosova, Eugeniy Mitrofanov, Toral Shah
Simplification of fully delay testable combinational circuits. IOLTS (2015)
Satyadev Ahlawat, Jaynarayan T. Tudu, Anzhela Yu. Matrosova, Virendra Singh
A New Scan Flip Flop Design to Eliminate Performance Penalty of Scan. ATS (2015)
Anzhela Yu. Matrosova, Sergey Ostanin, Irina Kirienko
Increasing Manufacturing Yield Using Partially Programmable Circuits with CLB Implementation of Incompletely Specified Boolean Function of the Corresponding Sub-Circuit. DDECS (2015)
Toral Shah, Anzhela Yu. Matrosova, Virendra Singh
PDF testability of a combinational circuit derived by covering ROBDD nodes using Invert-And-Or circuits. VDAT (2015)
Anzhela Yu. Matrosova, Valeriy B. Lipskii
Properties of pairs of test vectors detecting path delay faults in high performance VLSI logical circuits. Autom. Remote. Control. 76 (4) (2015)
Anzhela Yu. Matrosova, Valentina Andreeva, V. Tomkov
Fully delay and multiple stuck-at faults testable FSM design. EWDTS (2015)
Anzhela Yu. Matrosova, Eugeniy Mitrofanov, Elena Roumjantseva
Combinational part structure simplification of fully delay testable sequential circuit. EWDTS (2014)
Anzhela Yu. Matrosova, Dmitry Kudin, Ekaterina Nikolaeva
Combinational circuits without false paths. EWDTS (2014)
Anzhela Yu. Matrosova, Sergey Ostanin, Irina Kirienko, Virendra Singh
Partially programmable circuit design. EWDTS (2014)
Anzhela Yu. Matrosova, Sergey A. Ostanin, Virendra Singh
Detection of false paths in logical circuits by joint analysis of the AND/OR trees and SSBDD-graphs. Autom. Remote. Control. 74 (7) (2013)
Anzhela Yu. Matrosova, Sergey Ostanin, Alexey Melnikov, Virendra Singh
Observability calculation of state variable oriented to robust PDFs and LOC or LOS techniques. EWDTS (2013)
Anzhela Yu. Matrosova, Eugeniy Mitrofanov, Virendra Singh
Delay testable sequential circuit designs. EWDTS (2013)
Anzhela Yu. Matrosova, Ekaterina Nikolaeva, Dmitry Kudin, Virendra Singh
PDF testability of the circuits derived by special covering ROBDDs with gates. EWDTS (2013)
Anzhela Yu. Matrosova, Alexey Melnikov, Ruslan Mukhamedov, Virendra Singh
Selection of the state variables for partial enhanced scan techniques. EWDTS (2011)
Anzhela Yu. Matrosova, Valeriy B. Lipsky, Alexey Melnikov, Virendra Singh
Path delay faults and ENF. EWDTS (2010)
K. R. Vinutha, Virendra Singh, Anzhela Yu. Matrosova, Manoj Singh Gaur
Fault grading using Instruction-Execution graph. EWDTS (2010)
Anzhela Yu. Matrosova, Vladimir Ostrovsky, Ilya Levin, K. Nikitin
Designing FPGA based Self-Testing Checkers for m-out-of-n Codes. IOLTS (2003)
Anzhela Yu. Matrosova, Valentina Andreeva, Yu. Sedov
Survivable Discrete Circuits Design. IOLTW (2002)
Anzhela Yu. Matrosova, K. Nikitin, Olga Goloubeva
Totally Self-Checking FSM Design Based on Multilevel Synthesis Methods and FPGA Implemetation. IOLTW (2001)
Anzhela Yu. Matrosova, Sergey Ostanin, Ilya Levin
Survivable Self-Checking Sequential Circuits. DFT (2001)
Anzhela Yu. Matrosova, Ilya Levin, Sergey Ostanin
Self-checking Synchronous FSM Network Design with Low Overhead. VLSI Design 2000 (1) (2000)
Anzhela Yu. Matrosova, Sergey Ostanin
Self-Checking FSM Design with Observing only FSM Outputs. IOLTW (2000)