Binod Kumar

Publication Activity (10 Years)

Years Active: 2016-2022
Publications (10 Years): 33

Top Topics

Formal Verification

Error Detection

Hardware Designs

Top Venues

Publications

Binod Kumar, V. S. Vineesh, Puneet Nemade, Masahiro Fujita
Aries: A Semiformal Technique for Fine-Grained Bug Localization in Hardware Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (12) (2022)
Utsav Jana, Sourav Banerjee, Binod Kumar, Madhu B, Shankar Umapathi, Masahiro Fujita
Deep Learning-assisted Scan Chain Diagnosis with Different Fault Models during Manufacturing Test. ATS (2022)
Harsh Bhargav, Vineesh V. S., Binod Kumar, Virendra Singh
Enhancing Testbench Quality via Genetic Algorithm. MWSCAS (2021)
V. S. Vineesh, Binod Kumar, Rushikesh Shinde, Neelam Sharma, Masahiro Fujita, Virendra Singh
Enhanced Design Debugging With Assistance From Guidance-Based Model Checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (5) (2021)
Binod Kumar, Jay Adhaduk, Kanad Basu, Masahiro Fujita, Virendra Singh
A Methodology to Capture Fine-Grained Internal Visibility During Multisession Silicon Debug. IEEE Trans. Very Large Scale Integr. Syst. 28 (4) (2020)
Binod Kumar, Swapniel Thakur, Kanad Basu, Masahiro Fujita, Virendra Singh
A Low Overhead Methodology for Validating Memory Consistency Models in Chip Multiprocessors. VLSI Design (2020)
Nandan Kumar Jha, Sparsh Mittal, Binod Kumar, Govardhan Mattela
DeepPeep: Exploiting Design Ramifications to Decipher the Architecture of Compact DNNs. CoRR (2020)
Nandan Kumar Jha, Sparsh Mittal, Binod Kumar, Govardhan Mattela
DeepPeep: Exploiting Design Ramifications to Decipher the Architecture of Compact DNNs. ACM J. Emerg. Technol. Comput. Syst. 17 (1) (2020)
Binod Kumar, Kanad Basu, Masahiro Fujita, Virendra Singh
Post-Silicon Gate-Level Error Localization With Effective and Combined Trace Signal Selection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (1) (2020)
Binod Kumar, Akshay Kumar Jaiswal, V. S. Vineesh, Rushikesh Shinde
Analyzing Hardware Security Properties of Processors through Model Checking. VLSI Design (2020)
Saurabh Gangurde, Binod Kumar
A Unified Methodology for Hardware Obfuscation and IP Watermarking. VDAT (2019)
Binod Kumar, Masahiro Fujita, Virendra Singh
A Methodology for SAT-Based Electrical Error Debugging During Post-Silicon Validation. VLSI Design (2019)
Vineesh V. S., Binod Kumar, Rushikesh Shinde, Akshay Jaiswal, Harsh Bhargava, Virendra Singh
Orion: A Technique to Prune State Space Search Directions for Guidance-Based Formal Verification. ATS (2019)
Binod Kumar, Masahiro Fujita, Virendra Singh
SAT-based Silicon Debug of Electrical Errors under Restricted Observability Enhancement. J. Electron. Test. 35 (5) (2019)
Binod Kumar, Atul Kumar Bhosale, Masahiro Fujita, Virendra Singh
Validating Multi-Processor Cache Coherence Mechanisms under Diminished Observability. ATS (2019)
V. S. Vineesh, Binod Kumar, Jay Adhaduk
Identification of Effective Guidance Hints for Better Design Debugging by Formal Methods. VDAT (2019)
Vinay Kumar, Ankit Singh, Shubham Upadhyay, Binod Kumar
Power-Delay-Error-Efficient Approximate Adder for Error-Resilient Applications. J. Circuits Syst. Comput. 28 (10) (2019)
Binod Kumar, Kanad Basu, Virendra Singh
A Technique for Electrical Error Localization with Learning Methods During Post-silicon Debugging. IGSC (2018)
Ankit Jindal, Binod Kumar, Nitish Jindal, Masahiro Fujita, Virendra Singh
Silicon Debug with Maximally Expanded Internal Observability Using Nearest Neighbor Algorithm. ISVLSI (2018)
Ankit Jindal, Binod Kumar, Kanad Basu, Masahiro Fujita
ELURA: A Methodology for Post-Silicon Gate-Level Error Localization Using Regression Analysis. VLSI Design (2018)
Toral Shah, Anzhela Yu. Matrosova, Binod Kumar, Masahiro Fujita, Virendra Singh
Testing multiple stuck-at faults of ROBDD based combinational circuit design. LATS (2017)
Binod Kumar, Ankit Jindal, Masahiro Fujita, Virendra Singh
Post-silicon observability enhancement with topology based trace signal selection. LATS (2017)
Binod Kumar, Kanad Basu, Ankit Jindal, Masahiro Fujita, Virendra Singh
Improving post-silicon error detection with topological selection of trace signals. VLSI-SoC (2017)
Vinay Kumar, Krishna Lal Baishnab, Binod Kumar
A Novel Shared Active Pixel Architecture (SAPA) with Low Dark Current and High Fill-Factor (FF) for CMOS Image Sensors. J. Low Power Electron. 13 (3) (2017)
Binod Kumar, Kanad Basu, Masahiro Fujita, Virendra Singh
RTL level trace signal selection and coverage estimation during post-silicon validation. HLDVT (2017)
Binod Kumar, Ankit Jindal, Masahiro Fujita, Virendra Singh
Combining Restorability and Error Detection Ability for Effective Trace Signal Selection. ACM Great Lakes Symposium on VLSI (2017)
Binod Kumar, Kanad Basu, Ankit Jindal, Brajesh Pandey, Masahiro Fujita
A Formal Perspective on Effective Post-silicon Debug and Trace Signal Selection. VDAT (2017)
Binod Kumar, Ankit Jindal, Virendra Singh, Masahiro Fujita
A Methodology for Trace Signal Selection to Improve Error Detection in Post-Silicon Validation. VLSI Design (2017)
Binod Kumar, Ankit Jindal, Jaynarayan T. Tudu, Brajesh Pandey, Virendra Singh
Revisiting random access scan for effective enhancement of post-silicon observability. IOLTS (2017)
Binod Kumar, Ankit Jindal, Virendra Singh
A trace signal selection algorithm for improved post-silicon debug. EWDTS (2016)
Nirmal Kumar Boran, Rameshwar Prasad Meghwal, Kuldeep Sharma, Binod Kumar, Virendra Singh
Performance modelling of heterogeneous ISA multicore architectures. EWDTS (2016)
Binod Kumar, Boda Nehru, Brajesh Pandey, Virendra Singh, Jaynarayan T. Tudu
A technique for low power, stuck-at fault diagnosable and reconfigurable scan architecture. EWDTS (2016)
Binod Kumar, Boda Nehru, Brajesh Pandey, Jaynarayan T. Tudu
Skip-scan: A methodology for test time reduction. VDAT (2016)