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Toral Shah
ORCID
Publication Activity (10 Years)
Years Active: 2015-2018
Publications (10 Years): 7
Top Topics
Logic Circuits
Destination Node
Multiple Faults
Circuit Design
Top Venues
EWDTS
IOLTS
LATS
J. Electron. Test.
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Publications
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Toral Shah
,
Anzhela Yu. Matrosova
,
Masahiro Fujita
,
Virendra Singh
Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design.
J. Electron. Test.
34 (1) (2018)
Toral Shah
,
Anzhela Yu. Matrosova
,
Binod Kumar
,
Masahiro Fujita
,
Virendra Singh
Testing multiple stuck-at faults of ROBDD based combinational circuit design.
LATS
(2017)
Toral Shah
,
Anzhela Yu. Matrosova
,
Virendra Singh
Test pattern generation to detect multiple faults in ROBDD based combinational circuits.
IOLTS
(2017)
Toral Shah
,
Virendra Singh
,
Anzhela Yu. Matrosova
ROBDD based path delay fault testable combinational circuit synthesis.
EWDTS
(2016)
Anzhela Yu. Matrosova
,
Eugeniy Mitrofanov
,
Toral Shah
Multiple stuck-at fault testability of a combinational circuit derived by covering ROBDD nodes by Invert-And-Or sub-circuits.
EWDTS
(2015)
Anzhela Yu. Matrosova
,
Eugeniy Mitrofanov
,
Toral Shah
Simplification of fully delay testable combinational circuits.
IOLTS
(2015)
Toral Shah
,
Anzhela Yu. Matrosova
,
Virendra Singh
PDF testability of a combinational circuit derived by covering ROBDD nodes using Invert-And-Or circuits.
VDAT
(2015)