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A Methodology for SAT-Based Electrical Error Debugging During Post-Silicon Validation.

Binod KumarMasahiro FujitaVirendra Singh
Published in: VLSI Design (2019)
Keyphrases
  • error rate
  • answer set programming
  • low cost
  • high speed
  • transmission line
  • reinforcement learning
  • knowledge representation
  • sat solvers
  • constraint propagation