Satyadev Ahlawat

Publication Activity (10 Years)

Years Active: 2015-2024
Publications (10 Years): 30

Top Topics

Countermeasures

Top Venues

Publications

Gaurav Kumar, Anjum Riaz, Pardeep Kumar, Yamuna Prasad, Satyadev Ahlawat
On Evaluating Test Response Obfuscation and Encryption Countermeasures. IOLTS (2024)
Aditi Gupta, Adeiza James Onumanyi, Satyadev Ahlawat, Yamuna Prasad, Virendra Singh, Adnan M. Abu-Mahfouz
DAT: A robust Discriminant Analysis-based Test of unimodality for unknown input distributions. Pattern Recognit. Lett. 182 (2024)
Aditi Gupta, Sukanya Gupta, Adeiza James Onumanyi, Satyadev Ahlawat, Yamuna Prasad, Virendra Singh
A-TSPD: autonomous-two stage algorithm for robust peak detection in online time series. Clust. Comput. 27 (4) (2024)
Mahendra Gurve, Sankar Behera, Satyadev Ahlawat, Yamuna Prasad
MisGUIDE : Defense Against Data-Free Deep Learning Model Extraction. CoRR (2024)
Gaurav Kumar, Anjum Riaz, Yamuna Prasad, Satyadev Ahlawat
On Evaluating the Security of Dynamic Scan Obfuscation Scheme. IOLTS (2023)
Anjum Riaz, Gaurav Kumar, Pardeep Kumar, Yamuna Prasad, Satyadev Ahlawat
On Protecting IJTAG using an Inherently Secure SIB. VLSI-SoC (2023)
Aditi Gupta, Adeiza James Onumanyi, Satyadev Ahlawat, Yamuna Prasad, Virendra Singh
TSPD: A Robust Online Time Series Two-Stage Peak Detection Algorithm. SOSE (2023)
Gaurav Kumar, Anjum Riaz, Yamuna Prasad, Satyadev Ahlawat
On Enhancing the Security of Streaming Scan Network Architecture. ATS (2023)
Gaurav Kumar, Anjum Riaz, Yamuna Prasad, Satyadev Ahlawat
On Attacking Locking SIB based IJTAG Architecture. ACM Great Lakes Symposium on VLSI (2022)
Gaurav Kumar, Anjum Riaz, Yamuna Prasad, Satyadev Ahlawat
A New Access Protocol for Elevating the Security of IJTAG Network. ATS (2022)
Gaurav Kumar, Anuj Kumar, Satyadev Ahlawat, Yamuna Prasad
Low Cost Implementation of Deep Neural Network on Hardware. VDAT (2022)
Gaurav Kumar, Anjum Riaz, Yamuna Prasad, Satyadev Ahlawat
Power Analysis Attack on Locking SIB based IJTAG Achitecture. VLSI-SoC (2022)
Yogendra Sao, Anjum Riaz, Satyadev Ahlawat, Sk Subidh Ali
Evaluating Security of New Locking SIB-based Architectures. ETS (2022)
Gaurav Kumar, Anjum Riaz, Yamuna Prasad, Satyadev Ahlawat
On Attacking IJTAG Architecture based on Locking SIB with Security LFSR. IOLTS (2022)
Anjum Riaz, Gaurav Kumar, Jaynarayan T. Tudu, Satyadev Ahlawat
On Protecting IJTAG from Data Sniffing and Alteration Attacks. ISVLSI (2022)
Jaynarayan T. Tudu, Satyadev Ahlawat, Sonali Shukla, Virendra Singh
A Framework for Configurable Joint-Scan Design-for-Test Architecture. J. Electron. Test. 37 (5) (2021)
Satyadev Ahlawat, Jaynarayan T. Tudu, Manoj Singh Gaur, Masahiro Fujita, Virendra Singh
Preventing Scan Attack through Test Response Encryption. DFT (2019)
Satyadev Ahlawat, Kailash Ahirwar, Jaynarayan T. Tudu, Masahiro Fujita, Virendra Singh
Securing Scan through Plain-text Restriction. IOLTS (2019)
Darshit Vaghani, Satyadev Ahlawat, Jaynarayan T. Tudu, Masahiro Fujita, Virendra Singh
On Securing Scan Design Through Test Vector Encryption. ISCAS (2018)
Satyadev Ahlawat, Darshit Vaghani, Naveen Bazard, Virendra Singh
Using MISR as Countermeasure Against Scan-Based Side-Channel Attacks. EWDTS (2018)
Nihar Hage, Satyadev Ahlawat, Virendra Singh
In-situ Monitoring for Slack Time Violation Without Performance Penalty. ISCAS (2018)
Satyadev Ahlawat, Darshit Vaghani, Rohini Gulve, Virendra Singh
A low cost technique for scan chain diagnosis. ISCAS (2017)
Satyadev Ahlawat, Darshit Vaghani, Jaynarayan T. Tudu, Virendra Singh
On Securing Scan Design from Scan-Based Side-Channel Attacks. ATS (2017)
Satyadev Ahlawat, Darshit Vaghani, Virendra Singh
An efficient test technique to prevent scan-based side-channel attacks. ETS (2017)
Satyadev Ahlawat, Darshit Vaghani, Jaynarayan T. Tudu, Ashok Suhag
A Cost Effective Technique for Diagnosis of Scan Chain Faults. VDAT (2017)
Satyadev Ahlawat, Darshit Vaghani, Virendra Singh
Preventing scan-based side-channel attacks through key masking. DFT (2017)
Satyadev Ahlawat, Jaynarayan T. Tudu, Anzhela Yu. Matrosova, Virendra Singh
A high performance scan flip-flop design for serial and mixed mode scan test. IOLTS (2016)
Satyadev Ahlawat, Darshit Vaghani, Rohini Gulve, Virendra Singh
Enabling LOS delay test with slow scan enable. EWDTS (2016)
Satyadev Ahlawat, Jaynarayan T. Tudu
On minimization of test power through modified scan flip-flop. VDAT (2016)
Jaynarayan T. Tudu, Satyadev Ahlawat
Guided shifting of test pattern to minimize test time in serial scan. VDAT (2016)
Satyadev Ahlawat, Jaynarayan T. Tudu, Anzhela Yu. Matrosova, Virendra Singh
A New Scan Flip Flop Design to Eliminate Performance Penalty of Scan. ATS (2015)