Valentina Andreeva

Publication Activity (10 Years)

Years Active: 2002-2022
Publications (10 Years): 7

Top Topics

Hierarchical Decomposition

Top Venues

Publications

Andrey Laputenko, Nina Yevtushenko, Valentina Andreeva, Anzhela Yu. Matrosova
Deriving FSM-based tests using $a, b-\text{faults}$ for Logic Circuits. ISVLSI (2022)
Anjela Yu. Matrosova, Valentina Andreeva, V. Tychinskiy
SAT Solvers Application of Deriving All Test Pairs Detecting Robust Testable PDFs. EWDTS (2021)
Anjela Yu. Matrosova, Valentina Andreeva, V. Tychinskiy
Deriving Low Power Test Sequences Detecting Robust Testable PDFs. EWDTS (2019)
Sergey Ostanin, Valentina Andreeva, Natalia Butorina, D. Tretyakov
Fault-Tolerant Synchronous FSM Network Design for Path Delay Faults. EWDTS (2018)
Valentina Andreeva, Semyon Chernyshov
Finding the shortest transfer sequence of sequential circuit based on simplified ROBDDs. EWDTS (2017)
Anjela Yu. Matrosova, Sergey Ostanin, Valentina Andreeva
Patching circuit design based on reserved CLBs. AQTR (2016)
Anzhela Yu. Matrosova, Valentina Andreeva, Alexey Melnikov
ROBDDs application for finding the shortest transfer sequence of sequential circuit or only revealing existence of this sequence without deriving the sequence itself. EWDTS (2016)
Anzhela Yu. Matrosova, Valentina Andreeva, V. Tomkov
Fully delay and multiple stuck-at faults testable FSM design. EWDTS (2015)
Valentina Andreeva, Kirill A. Sorudeykin
Decomposition tree - based compaction procedure with iteration steps for interconversional layouts of tasks. EWDTS (2014)
Valentina Andreeva, Kirill A. Sorudeykin
A research of heuristic optimization approaches to the test set compaction procedure based on a decomposition tree for combinational circuits. EWDTS (2013)
Valentina Andreeva
Test set compaction procedure for combinational circuits based on decomposition tree. EWDTS (2011)
Valentina Andreeva
Test minimization technique for multiple stuck-at faults of combinational circuit. EWDTS (2010)
Anzhela Yu. Matrosova, Valentina Andreeva, Yu. Sedov
Survivable Discrete Circuits Design. IOLTW (2002)