Adit D. Singh

Publication Activity (10 Years)

Years Active: 1978-2023
Publications (10 Years): 37

Top Venues

VTS

VLSI Design

ETS

ATS

Publications

Adit D. Singh
Silent Error Corruption: The New Reliability and Test Challenge. LATS (2023)
Adit D. Singh, Sreejit Chakravarty, George Papadimitriou, Dimitris Gizopoulos
Silent Data Errors: Sources, Detection, and Modeling. VTS (2023)
Wendong Wang, Adit D. Singh, Ujjwal Guin
A Systematic Bit Selection Method for Robust SRAM PUFs. J. Electron. Test. 38 (3) (2022)
Adit D. Singh
Understanding Vmin Failures for Improved Testing of Timing Marginalities. ITC (2022)
Sujay Pandey, Zhiwei Liao, Shreyas Nandi, Suriyaprakash Natarajan, Arani Sinha, Adit D. Singh, Abhijit Chatterjee
Two Pattern Timing Tests Capturing Defect-Induced Multi-Gate Delay Impact of Shorts. VTS (2021)
Sabyasachi Deyati, Barry J. Muldrey, Adit D. Singh, Abhijit Chatterjee
High Resolution Pulse Propagation Driven Trojan Detection in Digital Systems. J. Electron. Test. 37 (1) (2021)
Prattay Chowdhury, Ujjwal Guin, Adit D. Singh, Vishwani D. Agrawal
Estimating Operational Age of an Integrated Circuit. J. Electron. Test. 37 (1) (2021)
Ilia Polian, Jens Anders, Steffen Becker, Paolo Bernardi, Krishnendu Chakrabarty, Nourhan Elhamawy, Matthias Sauer, Adit D. Singh, Matteo Sonza Reorda, Stefan Wagner
Exploring the Mysteries of System-Level Test. CoRR (2021)
Ilia Polian, Jens Anders, Steffen Becker, Paolo Bernardi, Krishnendu Chakrabarty, Nourhan Elhamawy, Matthias Sauer, Adit D. Singh, Matteo Sonza Reorda, Stefan Wagner
Exploring the Mysteries of System-Level Test. ATS (2020)
Wendong Wang, Ujjwal Guin, Adit D. Singh
Aging-Resilient SRAM-based True Random Number Generator for Lightweight Devices. J. Electron. Test. 36 (3) (2020)
Sujay Pandey, Zhiwei Liao, Shreyas Nandi, Sanya Gupta, Suriyaprakash Natarajan, Arani Sinha, Adit D. Singh, Abhijit Chatterjee
SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts. ITC (2020)
Wendong Wang, Ujjwal Guin, Adit D. Singh
A Zero-Cost Detection Approach for Recycled ICs using Scan Architecture. VTS (2020)
Ujjwal Guin, Wendong Wang, Charles Harper, Adit D. Singh
Detecting Recycled SoCs by Exploiting Aging Induced Biases in Memory Cells. HOST (2019)
Adit D. Singh
An Adaptive Approach to Minimize System Level Tests Targeting Low Voltage DVFS Failures. ITC (2019)
Prattay Chowdhury, Ujjwal Guin, Adit D. Singh, Vishwani D. Agrawal
Two-Pattern ∆IDDQ Test for Recycled IC Detection. VLSI Design (2019)
Ujjwal Guin, Ziqi Zhou, Adit D. Singh
Robust Design-for-Security Architecture for Enabling Trust in IC Manufacturing and Test. IEEE Trans. Very Large Scale Integr. Syst. 26 (5) (2018)
Ujjwal Guin, Adit D. Singh, Mahabubul Alam, Janice Canedo, Anthony Skjellum
A Secure Low-Cost Edge Device Authentication Scheme for the Internet of Things. VLSI Design (2018)
Jan Burchard, Dominik Erb, Sudhakar M. Reddy, Adit D. Singh, Bernd Becker
On the Generation of Waveform-Accurate Hazard and Charge-Sharing Aware Tests for Transistor Stuck-Off Faults in CMOS Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (10) (2018)
Wendong Wang, Adit D. Singh, Ujjwal Guin, Abhijit Chatterjee
Exploiting power supply ramp rate for calibrating cell strength in SRAM PUFs. LATS (2018)
Daniel Kraak, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Francky Catthoor, Abhijit Chatterjee, Adit D. Singh, Hans-Joachim Wunderlich, Naghmeh Karimi
Device aging: A reliability and security concern. ETS (2018)
Jan Burchard, Dominik Erb, Sudhakar M. Reddy, Adit D. Singh, Bernd Becker
Efficient SAT-based generation of hazard-activated TSOF tests. VTS (2017)
Jan Burchard, Dominik Erb, Adit D. Singh, Sudhakar M. Reddy, Bernd Becker
Fast and waveform-accurate hazard-aware SAT-based TSOF ATPG. DATE (2017)
Ujjwal Guin, Ziqi Zhou, Adit D. Singh
A novel design-for-security (DFS) architecture to prevent unauthorized IC overproduction. VTS (2017)
Ankush Srivastava, Virendra Singh, Adit D. Singh, Kewal K. Saluja
Identifying high variability speed-limiting paths under aging. LATS (2017)
Ankush Srivastava, Virendra Singh, Adit D. Singh, Kewal K. Saluja
A Reliability-Aware Methodology to Isolate Timing-Critical Paths under Aging. J. Electron. Test. 33 (6) (2017)
Ankush Srivastava, Adit D. Singh, Virendra Singh, Kewal K. Saluja
Exploiting path delay test generation to develop better TDF tests for small delay defects. ITC (2017)
Bernd Becker, Adit D. Singh
Best paper. ETS (2017)
Sujay Pandey, Sabyasachi Deyati, Adit D. Singh, Abhijit Chatterjee
Noise-Resilient SRAM Physically Unclonable Function Design for Security. ATS (2016)
Adit D. Singh
Adaptive Test Methods for High IC Quality and Reliability. VLSI Design (2016)
Adit D. Singh
Cell Aware and stuck-open tests. ETS (2016)
Adit D. Singh
Scan based two-pattern tests: should they target opens instead of TDFs? LATS (2015)
Adit D. Singh
Embedded Tutorial ET1: Better-than-Worst-Case Timing Designs. VLSI Design (2015)
Manuel J. Barragan, Gildas Léger, Florence Azaïs, Ronald D. Blanton, Adit D. Singh, Stephen Sunter
Special session: Hot topics: Statistical test methods. VTS (2015)
Sabyasachi Deyati, Barry John Muldrey, Adit D. Singh, Abhijit Chatterjee
Challenge Engineering and Design of Analog Push Pull Amplifier Based Physically Unclonable Function for Hardware Security. ATS (2015)
Yu Wang, Adit D. Singh
An Efficient Transition Detector Exploiting Charge Sharing. VLSI Design (2015)
Virendra Singh, Adit D. Singh, Kewal K. Saluja
A Methodology for Identifying High Timing Variability Paths in Complex Designs. ATS (2015)
Chao Han, Adit D. Singh
Testing cross wire opens within complex gates. VTS (2015)
Adit D. Singh
Error detection and recovery in better-than-worst-case timing designs. ETS (2014)
Sabyasachi Deyati, Barry John Muldrey, Adit D. Singh, Abhijit Chatterjee
High Resolution Pulse Propagation Driven Trojan Detection in Digital Logic: Optimization Algorithms and Infrastructure. ATS (2014)
Jie Zou, Chao Han, Adit D. Singh
Timing Evaluation Tests for Scan Enable Signals with Application to TDF Testing. ATS (2014)
Ravi Kanth Uppu, Ravi Tej Uppu, Adit D. Singh, Ilia Polian
Better-than-Worst-Case Timing Design with Latch Buffers on Short Paths. VLSI Design (2014)
Chao Han, Adit D. Singh
Improving CMOS open defect coverage using hazard activated tests. VTS (2014)
Chao Han, Adit D. Singh
On the testing of hazard activated open defects. ITC (2014)
Ilia Polian, Jie Jiang, Adit D. Singh
Detection conditions for errors in self-adaptive better-than-worst-case designs. ETS (2014)
Jayaram Natarajan, Sahil Kapoor, Debesh Bhatta, Abhijit Chatterjee, Adit D. Singh
Timing Variation Adaptive Pipeline Design: Using Probabilistic Activity Completion Sensing with Backup Error Resilience. VLSI Design (2014)
Hans A. R. Manhaeve, Pete Harrod, Adit D. Singh, Chintan Patel, Ralf Arnolc, Davide Appello
Current testing: Dead or alive? ETS (2013)
Janusz Rajski, Miodrag Potkonjak, Adit D. Singh, Abhijit Chatterjee, Zain Navabi, Matthew R. Guthaus, Sezer Gören
Embedded tutorials: Embedded tutorial 1: Cell-aware test-from gates to transistors. VLSI-SoC (2013)
Jennifer Dworak, Ronald Shawn Blanton, Masahiro Fujita, Kazumi Hatayama, Naghmeh Karimi, Michail Maniatakos, Antonis M. Paschalis, Adit D. Singh, Tian Xia
Special session 4B: Elevator talks. VTS (2013)
Ravi Tej Uppu, Ravi Kanth Uppu, Adit D. Singh, Abhijit Chatterjee
A High Throughput Multiplier Design Exploiting Input Based Statistical Distribution in Completion Delays. VLSI Design (2013)
Chao Han, Adit D. Singh
Hazard Initialized LOC Tests for TDF Undetectable CMOS Open Defects. Asian Test Symposium (2013)
Mohammed Shayan, Virendra Singh, Adit D. Singh, Masahiro Fujita
SEU Tolerant Robust Latch Design. VDAT (2012)
Mohammed Shayan, Virendra Singh, Adit D. Singh, Masahiro Fujita
SEU tolerant robust memory cell design. IOLTS (2012)
Xi Qian, Chao Han, Adit D. Singh
Detection of gate-oxide defects with timing tests at reduced power supply. VTS (2012)
Jayaram Natarajan, Joshua W. Wells, Abhijit Chatterjee, Adit D. Singh
Distributed Comparison Test Driven Multiprocessor Speed-Tuning: Targeting Performance Gains under Extreme Process Variations. Asian Test Symposium (2011)
Kautalya Mishra, Ahmed Faraz, Adit D. Singh
Path Delay Tuning for Performance Gain in the Face of Random Manufacturing Variations. VLSI Design (2011)
Mohammed Abdul Razzaq, Virendra Singh, Adit D. Singh
SSTKR: Secure and Testable Scan Design through Test Key Randomization. Asian Test Symposium (2011)
Xi Qian, Adit D. Singh, Abhijit Chatterjee
Diagnosing Multiple Slow Gates for Performance Tuning in the Face of Extreme Process Variations. Asian Test Symposium (2011)
Erik Jan Marinissen, Adit D. Singh, Dan Glotter, Marco Esposito, John M. Carulli Jr., Amit Nahar, Kenneth M. Butler, Davide Appello, Chris Portelli
Adapting to adaptive testing. DATE (2010)
Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Hideo Fujiwara, Adit D. Singh
On Minimization of Test Application Time for RAS. VLSI Design (2010)
Balapradeep Gadamsetti, Adit D. Singh
Current Sensing Completion Detection for high speed and area efficient arithmetic. APCCAS (2010)
Adit D. Singh, Chao Han, Xi Qian
An output compression scheme for handling X-states from over-clocked delay tests. VTS (2010)
Xi Qian, Adit D. Singh
Distinguishing Resistive Small Delay Defects from Random Parameter Variations. Asian Test Symposium (2010)
Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Adit D. Singh
Modified T-Flip-Flop based scan cell for RAS. ETS (2010)
A. Abhishek, Amanulla Khan, Virendra Singh, Kewal K. Saluja, Adit D. Singh
Test application time minimization for RAS using basis optimization of column decoder. ISCAS (2010)
Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh
Post-Manufacture Tuning for Nano-CMOS Yield Recovery Using Reconfigurable Logic. IEEE Trans. Very Large Scale Integr. Syst. 18 (4) (2010)
Amit Mishra, Nidhi Sinha, Satdev, Virendra Singh, Sreejit Chakravarty, Adit D. Singh
Modified Scan Flip-Flop for Low Power Testing. Asian Test Symposium (2010)
K. G. Deepak, Robinson Reyna, Virendra Singh, Adit D. Singh
Leveraging Partially Enhanced Scan for Improved Observability in Delay Fault Testing. Asian Test Symposium (2009)
Abhijit Chatterjee, Jacob A. Abraham, Adit D. Singh, Elie Maricau, Rakesh Kumar, Christos A. Papachristou
Panel: Realistic low power design: Let errors occur and correct them later or mitigate errors via design guardbanding and process control?. IOLTS (2009)
Sreekumar Menon, Adit D. Singh, Vishwani D. Agrawal
Output Hazard-Free Transition Delay Fault Test Generation. VTS (2009)
Adit D. Singh
A Defect Tolerant and Performance Tunable Gate Architecture for End-of-Roadmap CMOS. DFT (2009)
Maryam Ashouei, Adit D. Singh, Abhijit Chatterjee
Reconfiguring CMOS as Pseudo N/PMOS for Defect Tolerance in Nano-Scale CMOS. VLSI Design (2008)
Adit D. Singh
Scan Based Testing of Dual/Multi Core Processors for Small Delay Defects. ITC (2008)
Adit D. Singh
Scan Delay Testing of Nanometer SoCs. VLSI Design (2008)
Gefu Xu, Adit D. Singh
Flip-flop Selection to Maximize TDF Coverage with Partial Enhanced Scan. ATS (2007)
Gefu Xu, Adit D. Singh
Achieving high transition delay fault coverage with partial DTSFF scan chains. ITC (2007)
Gefu Xu, Adit D. Singh
Scan cell design for launch-on-shift delay tests with slow scan enable. IET Comput. Digit. Tech. 1 (3) (2007)
Gefu Xu, Adit D. Singh
Delay Test Scan Flip-Flop: DFT for High Coverage Delay Testing. VLSI Design (2007)
Maryam Ashouei, Muhammad Mudassar Nisar, Abhijit Chatterjee, Adit D. Singh, Abdulkadir Utku Diril
Probabilistic Self-Adaptation of Nanoscale CMOS Circuits: Yield Maximization under Increased Intra-Die Variations. VLSI Design (2007)
Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh
Analysis and Optimization of Nanometer CMOS Circuits for Soft-Error Tolerance. IEEE Trans. Very Large Scale Integr. Syst. 14 (5) (2006)
Thomas S. Barnett, Matt Grady, Kathleen G. Purdy, Adit D. Singh
Combining Negative Binomial and Weibull Distributions for Yield and Reliability Prediction. IEEE Des. Test Comput. 23 (2) (2006)
Adit D. Singh, Gefu Xu
Output Hazard-Free Transition Tests for Silicon Calibrated Scan Based Delay Testing. VTS (2006)
Bashir M. Al-Hashimi, Dimitris Gizopoulos, Manoj Sachdev, Adit D. Singh
New JETTA Editors, 2006. J. Electron. Test. 22 (1) (2006)
Haihua Yan, Adit D. Singh
A New Delay Test Based on Delay Defect Detection Within Slack Intervals (DDSI). IEEE Trans. Very Large Scale Integr. Syst. 14 (11) (2006)
Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De, T. M. Mak
Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware Design. VLSI Design (2006)
Gefu Xu, Adit D. Singh
Low Cost Launch-on-Shift Delay Test with Slow Scan Enable. ETS (2006)
Xiangdong Xuan, Adit D. Singh, Abhijit Chatterjee
Lifetime Prediction and Design-for-Reliability of IC Interconnections with Electromigration Induced Degradation in the Presence of Manufacturing Defects. J. Electron. Test. 22 (4-6) (2006)
Haihua Yan, Gefu Xu, Adit D. Singh
Low Voltage Test in Place of Fast Clock in DDSI Delay Test. ISQED (2005)
Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh
Design of Adaptive Nanometer Digital Systems for Effective Control of Soft Error Tolerance. VTS (2005)
Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh
Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages. IEEE Trans. Very Large Scale Integr. Syst. 13 (9) (2005)
Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De
A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nanometer CMOS. ICCD (2005)
Anand S. Mudlapur, Vishwani D. Agrawal, Adit D. Singh
A random access scans architecture to reduce hardware overhead. ITC (2005)
Adit D. Singh
A self-timed structural test methodology for timing anomalies due to defects and process variations. ITC (2005)
Haihua Yan, Adit D. Singh, Gefu Xu
Delay Defect Characterization Using Low Voltage Test. Asian Test Symposium (2005)
Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh
Pseudo Dual Supply Voltage Domino Logic Design. J. Low Power Electron. 1 (2) (2005)
Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh
Low-power domino circuits using NMOS pull-up on off-critical paths. ASP-DAC (2005)
Haihua Yan, Adit D. Singh
A Delay Test to Differentiate Resistive Interconnect Faults from Weak Transistor Defects. VLSI Design (2005)
Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh
Level-Shifter Free Design of Low Power Dual Supply Voltage CMOS Circuits Using Dual Threshold Voltages. VLSI Design (2005)
Adit D. Singh
T2: Statistical Methods for VLSI Test and Burn-in Optimization. Asian Test Symposium (2005)
Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh
Sizing CMOS Circuits for Increased Transient Error Tolerance. IOLTS (2004)
Haihua Yan, Adit D. Singh
Reduce Yield Loss in Delay Defect Detection in Slack Interval. Asian Test Symposium (2004)

Adit D. Singh.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Adit D. Singh